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Searched refs:refdiv (Results 1 – 2 of 2) sorted by relevance

/optee_os/core/drivers/clk/
H A Dclk-stm32mp21.c1390 static void stm32mp2_a35_pll1_config(uint32_t fbdiv, uint32_t refdiv, in stm32mp2_a35_pll1_config() argument
1394 SHIFT_U32(refdiv, in stm32mp2_a35_pll1_config()
2075 uint32_t refdiv = 0; in clk_get_pll1_fvco_rate() local
2081 refdiv = (reg & CA35SS_SSC_PLL_FREQ1_REFDIV_MASK) >> in clk_get_pll1_fvco_rate()
2084 if (!refdiv || MUL_OVERFLOW(refclk, fbdiv, &freq)) in clk_get_pll1_fvco_rate()
2087 return freq / refdiv; in clk_get_pll1_fvco_rate()
2167 uint32_t refdiv = 0; in clk_get_pll_fvco() local
2173 refdiv = io_read32(pllxcfgr2) & RCC_PLLxCFGR2_FREFDIV_MASK; in clk_get_pll_fvco()
2175 assert(refdiv); in clk_get_pll_fvco()
2183 denominator = SHIFT_U64(refdiv, 24); in clk_get_pll_fvco()
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H A Dclk-stm32mp25.c1408 static void stm32mp2_a35_pll1_config(uint32_t fbdiv, uint32_t refdiv, in stm32mp2_a35_pll1_config() argument
1412 SHIFT_U32(refdiv, in stm32mp2_a35_pll1_config()
2068 uint32_t refdiv = 0; in clk_get_pll1_fvco_rate() local
2074 refdiv = (reg & CA35SS_SSC_PLL_FREQ1_REFDIV_MASK) >> in clk_get_pll1_fvco_rate()
2077 if (!refdiv || MUL_OVERFLOW(refclk, fbdiv, &freq)) in clk_get_pll1_fvco_rate()
2080 return freq / refdiv; in clk_get_pll1_fvco_rate()
2160 uint32_t refdiv = 0; in clk_get_pll_fvco() local
2166 refdiv = io_read32(pllxcfgr2) & RCC_PLLxCFGR2_FREFDIV_MASK; in clk_get_pll_fvco()
2168 assert(refdiv); in clk_get_pll_fvco()
2176 denominator = SHIFT_U64(refdiv, 24); in clk_get_pll_fvco()
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