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Searched refs:postdiv2 (Results 1 – 2 of 2) sorted by relevance

/optee_os/core/drivers/clk/
H A Dclk-stm32mp21.c1391 uint32_t postdiv1, uint32_t postdiv2) in stm32mp2_a35_pll1_config() argument
1402 SHIFT_U32(postdiv2, in stm32mp2_a35_pll1_config()
2096 uint32_t postdiv2 = 0; in clk_stm32_pll1_get_rate() local
2101 postdiv2 = (reg & CA35SS_SSC_PLL_FREQ2_POSTDIV2_MASK) >> in clk_stm32_pll1_get_rate()
2104 if (!postdiv1 || !postdiv2) in clk_stm32_pll1_get_rate()
2107 dfout = clk_get_pll1_fvco_rate(prate) / (postdiv1 * postdiv2); in clk_stm32_pll1_get_rate()
2203 uint32_t postdiv2 = 0; in clk_stm32_pll_get_rate() local
2206 postdiv2 = io_read32(pllxcfgr7) & RCC_PLLxCFGR7_POSTDIV2_MASK; in clk_stm32_pll_get_rate()
2209 !postdiv1 || !postdiv2) in clk_stm32_pll_get_rate()
2213 prate) / (postdiv1 * postdiv2); in clk_stm32_pll_get_rate()
H A Dclk-stm32mp25.c1409 uint32_t postdiv1, uint32_t postdiv2) in stm32mp2_a35_pll1_config() argument
1420 SHIFT_U32(postdiv2, in stm32mp2_a35_pll1_config()
2089 uint32_t postdiv2 = 0; in clk_stm32_pll1_get_rate() local
2094 postdiv2 = (reg & CA35SS_SSC_PLL_FREQ2_POSTDIV2_MASK) >> in clk_stm32_pll1_get_rate()
2097 if (!postdiv1 || !postdiv2) in clk_stm32_pll1_get_rate()
2100 dfout = clk_get_pll1_fvco_rate(prate) / (postdiv1 * postdiv2); in clk_stm32_pll1_get_rate()
2196 uint32_t postdiv2 = 0; in clk_stm32_pll_get_rate() local
2199 postdiv2 = io_read32(pllxcfgr7) & RCC_PLLxCFGR7_POSTDIV2_MASK; in clk_stm32_pll_get_rate()
2202 !postdiv1 || !postdiv2) in clk_stm32_pll_get_rate()
2206 prate) / (postdiv1 * postdiv2); in clk_stm32_pll_get_rate()