| /optee_os/core/drivers/ |
| H A D | bcm_sotp.c | 88 io_setbits32((bcm_sotp_base + SOTP_PROG_CONTROL), in bcm_iproc_sotp_mem_read()
99 io_setbits32((bcm_sotp_base + SOTP_PROG_CONTROL), in bcm_iproc_sotp_mem_read()
110 io_setbits32((bcm_sotp_base + SOTP_CTRL_0), SOTP_CTRL_0__START); in bcm_iproc_sotp_mem_read()
137 io_setbits32((bcm_sotp_base + SOTP_STATUS_1), SOTP_STATUS_1__CMD_DONE); in bcm_iproc_sotp_mem_read()
182 io_setbits32(bcm_sotp_base + SOTP_PROG_CONTROL, in bcm_iproc_sotp_mem_write()
187 io_setbits32(bcm_sotp_base + SOTP_PROG_CONTROL, in bcm_iproc_sotp_mem_write()
211 io_setbits32(bcm_sotp_base + SOTP_CTRL_0, SOTP_CTRL_0__START); in bcm_iproc_sotp_mem_write()
223 io_setbits32(bcm_sotp_base + SOTP_STATUS_1, in bcm_iproc_sotp_mem_write()
253 io_setbits32(bcm_sotp_base + SOTP_CTRL_0, SOTP_CTRL_0__START); in bcm_iproc_sotp_mem_write()
264 io_setbits32(bcm_sotp_base + SOTP_STATUS_1, SOTP_STATUS_1__CMD_DONE); in bcm_iproc_sotp_mem_write()
|
| H A D | atmel_trng.c | 77 io_setbits32(trng_base + TRNG_CTRL, ctrl_val); in atmel_trng_reset()
79 io_setbits32(trng_base + TRNG_IER, 1); in atmel_trng_reset()
81 io_setbits32(trng_base + TRNG_CTRL, ctrl_val | 1); in atmel_trng_reset()
|
| H A D | ls_gpio.c | 69 io_setbits32(gpio_data_addr, PIN_SHIFT(gpio_pin)); in ls_gpio_set_value()
119 io_setbits32(gpio_dir_addr, PIN_SHIFT(gpio_pin)); in ls_gpio_set_direction()
168 io_setbits32(gpio_ier_addr, PIN_SHIFT(gpio_pin)); in gpio_set_interrupt()
233 io_setbits32(gpio_data->gpio_base + GPIOIBE, UINT32_MAX); in ls_gpio_init()
|
| H A D | imx_rngb.c | 90 io_setbits32(rng->base.va + RNG_CR, in irq_clear()
92 io_setbits32(rng->base.va + RNG_CMD, in irq_clear()
110 io_setbits32(rng->base.va + RNG_CR, RNG_CR_AR); in rng_seed()
|
| H A D | atmel_piobu.c | 128 io_setbits32(piobu_addr, SECUMOD_PIOBU_SOD); in secumod_gpio_set_value()
174 io_setbits32(piobu_addr, SECUMOD_PIOBU_OUTPUT); in secumod_gpio_set_direction()
218 io_setbits32(niepr_addr, SECUMOD_PIN_VAL(gpio_pin)); in secumod_gpio_set_interrupt()
336 io_setbits32(secumod_base + piobu_device->compat->of_nmpr, in secumod_cfg_input_pio()
341 io_setbits32(secumod_base + piobu_device->compat->of_wkpr, in secumod_cfg_input_pio()
|
| H A D | imx_ocotp.c | 39 io_setbits32(va + CCM_CCGR2, BM_CCM_CCGR2_OCOTP_CTRL); in ocotp_clock_enable()
46 io_setbits32(va + CCM_CCGRx_SET(CCM_CLOCK_DOMAIN_OCOTP), in ocotp_clock_enable()
54 io_setbits32(va + CCM_CCGRx_SET(CCM_CCRG_OCOTP), in ocotp_clock_enable()
|
| H A D | imx_snvs.c | 104 io_setbits32(base + SNVS_HPCOMR, SNVS_HPCOMR_MKS_EN); in set_mks_otpmk()
107 io_setbits32(base + SNVS_LPLR, SNVS_LPLR_MKS_HL); in set_mks_otpmk()
|
| H A D | zynqmp_csudma.c | 91 io_setbits32(dma + CSUDMA_CTRL_OFFSET, CSUDMA_CTRL_ENDIAN_MASK); in zynqmp_csudma_prepare()
93 io_setbits32(dma + CSUDMA_CTRL_OFFSET, CSUDMA_CTRL_ENDIAN_MASK); in zynqmp_csudma_prepare()
|
| H A D | atmel_rstc.c | 104 io_setbits32(rstc_base + RESET_OFFSET(id), BIT(RESET_BIT_POS(id))); in reset_assert()
169 io_setbits32(rstc_base + AT91_RSTC_GRSTR, in sam_rstc_usb_por()
|
| /optee_os/core/drivers/crypto/caam/hal/common/ |
| H A D | hal_jr.c | 41 io_setbits32(baseaddr + JRX_JRCFGR_LS, JRX_JRCFGR_LS_IMSK); in caam_hal_jr_reset()
142 io_setbits32(baseaddr + JRX_JRCFGR_LS, JRX_JRCFGR_LS_IMSK); in caam_hal_jr_disable_itr()
143 io_setbits32(baseaddr + JRX_JRINTR, JRX_JRINTR_JRI); in caam_hal_jr_disable_itr()
164 io_setbits32(baseaddr + JRX_JRINTR, JRX_JRINTR_JRI); in caam_hal_jr_check_ack_itr()
177 io_setbits32(baseaddr + JRX_JRCFGR_LS, JRX_JRCFGR_LS_IMSK); in caam_hal_jr_halt()
207 io_setbits32(baseaddr + JRX_JRCFGR_LS, JRX_JRCFGR_LS_IMSK); in caam_hal_jr_flush()
|
| H A D | hal_rng.c | 92 io_setbits32(baseaddr + TRNG_MCTL, TRNG_MCTL_PRGM | TRNG_MCTL_ACC); in caam_hal_rng_kick()
159 io_setbits32(baseaddr + TRNG_MCTL, TRNG_MCTL_ERR); in caam_hal_rng_kick()
|
| /optee_os/core/drivers/pm/imx/ |
| H A D | gpcv2.c | 28 io_setbits32(va + offset, GPC_PGC_PCG_MASK); in imx_gpcv2_set_core_pgc()
40 io_setbits32(va + GPC_CPU_PGC_SW_PUP_REQ, in imx_gpcv2_set_core1_pup_by_software()
|
| H A D | src.c | 65 io_setbits32(va + SRC_A7RCR1, in imx_src_release_secondary_core()
68 io_setbits32(va + SRC_SCR, SRC_SCR_CORE1_ENABLE_BIT(cpu) | in imx_src_release_secondary_core()
|
| /optee_os/core/arch/arm/plat-rzn1/ |
| H A D | psci.c | 78 io_setbits32(core_mmu_get_va(SYSCTRL_REG_RSTEN, MEM_AREA_IO_SEC, in psci_system_reset()
83 io_setbits32(core_mmu_get_va(SYSCTRL_REG_RSTCTRL, MEM_AREA_IO_SEC, in psci_system_reset()
|
| H A D | main.c | 102 io_setbits32(cm3_pwrctrl_reg, SYSCTRL_PWRCTRL_CM3_CLKEN_A); in rzn1_cm3_start()
103 io_setbits32(cm3_pwrctrl_reg, SYSCTRL_PWRCTRL_CM3_RSTN_A); in rzn1_cm3_start()
|
| /optee_os/core/drivers/crypto/caam/hal/imx_8m/ |
| H A D | hal_ctrl.c | 15 io_setbits32(baseaddr + MCFGR, MCFGR_WDE); in caam_hal_ctrl_init()
|
| /optee_os/core/drivers/crypto/caam/hal/imx_8ulp/ |
| H A D | hal_ctrl.c | 16 io_setbits32(baseaddr + MCFGR, MCFGR_WDE); in caam_hal_ctrl_init()
|
| H A D | hal_clk.c | 18 io_setbits32(pcc3_base + PCC_CAAM, PCC_ENABLE_CLOCK); in caam_hal_clk_enable()
|
| /optee_os/core/arch/arm/plat-stm32mp1/drivers/ |
| H A D | stm32mp1_syscfg.c | 109 io_setbits32(cmpcr_va + CMPENSETR_OFFSET, SYSCFG_CMPENSETR_MPU_EN); in enable_io_compensation()
142 io_setbits32(cmpcr_base + CMPENCLRR_OFFSET, SYSCFG_CMPENSETR_MPU_EN); in disable_io_compensation()
260 io_setbits32(base + SYSCFG_SRAM3ERASER, SYSCFG_SRAM3ERASER_SRAM3ER); in stm32mp_syscfg_erase_sram3()
|
| /optee_os/core/drivers/counter/ |
| H A D | stm32_stgen.c | 116 io_setbits32(stgen_d.base + STGENC_CNTCR, STGENC_CNTCR_EN); in stm32_stgen_pm_suspend()
155 io_setbits32(stgen_d.base + STGENC_CNTCR, STGENC_CNTCR_EN); in stm32_stgen_pm_resume()
254 io_setbits32(stgen_d.base + STGENC_CNTCR, STGENC_CNTCR_EN); in stgen_probe()
|
| /optee_os/core/arch/arm/plat-sunxi/ |
| H A D | psci.c | 127 io_setbits32(cpucfg + REG_CPUCFG_DBG_CTRL1, BIT32(core_idx)); in psci_cpu_on()
154 io_setbits32(base + REG_PRCM_CPU_PWROFF, BIT32(core_id)); in psci_cpu_off()
|
| /optee_os/core/drivers/crypto/caam/hal/imx_6_7/ |
| H A D | hal_ctrl.c | 29 io_setbits32(baseaddr + MCFGR, MCFGR_WDE); in caam_hal_ctrl_init()
|
| /optee_os/core/drivers/amd/ |
| H A D | ps_gpio_driver.c | 112 io_setbits32(ps->vbase + DIRM_OFFSET(bank), BIT(pin)); in ps_gpio_set_dir()
115 io_setbits32(ps->vbase + OUTEN_OFFSET(bank), BIT(pin)); in ps_gpio_set_dir()
170 io_setbits32(ps->vbase + offset, BIT(pin)); in ps_gpio_set_intr()
|
| /optee_os/core/arch/arm/plat-sam/ |
| H A D | sam_sfr.c | 36 io_setbits32(sam_sfr_base() + AT91_SFR_OHCIICR, in atmel_sfr_set_usb_suspend()
|
| /optee_os/core/arch/arm/plat-rockchip/ |
| H A D | platform_px30.c | 48 io_setbits32(fw_base + FIREWALL_DDR_FW_DDR_CON_REG, BIT(rgn)); in platform_secure_ddr_region()
|