Searched refs:RCC_XBAR0CFGR (Results 1 – 4 of 4) sorted by relevance
| /optee_os/core/drivers/clk/ |
| H A D | clk-stm32mp21.c | 583 _MUX_CFG(MUX_XBARSEL, RCC_XBAR0CFGR, 0, 4, MUX_NO_RDY),
1335 uintptr_t xbar0cfgr = priv->base + RCC_XBAR0CFGR; in stm32mp2_clk_xbar_on_hsi()
1679 uintptr_t xbar_cfgr = rcc_base + RCC_XBAR0CFGR + (0x4 * channel); in wait_xbar_sts()
1755 io_clrsetbits32(rcc_base + RCC_XBAR0CFGR + (0x4 * channel), in flexclkgen_config_channel()
1759 io_setbits32(rcc_base + RCC_XBAR0CFGR + (0x4 * channel), in flexclkgen_config_channel()
2258 address = rcc_base + RCC_XBAR0CFGR + (cfg->flex_id * 4); in clk_stm32_flexgen_get_parent()
2270 io_clrsetbits32(rcc_base + RCC_XBAR0CFGR + (channel), in clk_stm32_flexgen_set_parent()
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| H A D | clk-stm32mp25.c | 618 _MUX_CFG(MUX_XBARSEL, RCC_XBAR0CFGR, 0, 4, MUX_NO_RDY),
1353 uintptr_t xbar0cfgr = priv->base + RCC_XBAR0CFGR; in stm32mp2_clk_xbar_on_hsi()
1683 uintptr_t xbar_cfgr = rcc_base + RCC_XBAR0CFGR + (0x4 * channel); in wait_xbar_sts()
1759 io_clrsetbits32(rcc_base + RCC_XBAR0CFGR + (0x4 * channel), in flexclkgen_config_channel()
1763 io_setbits32(rcc_base + RCC_XBAR0CFGR + (0x4 * channel), in flexclkgen_config_channel()
2290 address = rcc_base + RCC_XBAR0CFGR + (cfg->flex_id * 4); in clk_stm32_flexgen_get_parent()
2301 io_clrsetbits32(rcc_base + RCC_XBAR0CFGR + (channel), in clk_stm32_flexgen_set_parent()
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| /optee_os/core/include/drivers/ |
| H A D | stm32mp21_rcc.h | 411 #define RCC_XBAR0CFGR U(0x1018) macro
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| H A D | stm32mp25_rcc.h | 472 #define RCC_XBAR0CFGR U(0x1018) macro
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