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Searched refs:RCC_PLLxCFGR7_POSTDIV2_MASK (Results 1 – 4 of 4) sorted by relevance

/optee_os/core/drivers/clk/
H A Dclk-stm32mp21.c1462 io_clrsetbits32(pllxcfgr7, RCC_PLLxCFGR7_POSTDIV2_MASK, in clk_stm32_pll_config_output()
1463 pllcfg[POSTDIV2] & RCC_PLLxCFGR7_POSTDIV2_MASK); in clk_stm32_pll_config_output()
2206 postdiv2 = io_read32(pllxcfgr7) & RCC_PLLxCFGR7_POSTDIV2_MASK; in clk_stm32_pll_get_rate()
H A Dclk-stm32mp25.c1480 io_clrsetbits32(pllxcfgr7, RCC_PLLxCFGR7_POSTDIV2_MASK, in clk_stm32_pll_config_output()
1481 pllcfg[POSTDIV2] & RCC_PLLxCFGR7_POSTDIV2_MASK); in clk_stm32_pll_config_output()
2199 postdiv2 = io_read32(pllxcfgr7) & RCC_PLLxCFGR7_POSTDIV2_MASK; in clk_stm32_pll_get_rate()
/optee_os/core/include/drivers/
H A Dstm32mp21_rcc.h1206 #define RCC_PLLxCFGR7_POSTDIV2_MASK GENMASK_32(2, 0) macro
H A Dstm32mp25_rcc.h1539 #define RCC_PLLxCFGR7_POSTDIV2_MASK GENMASK_32(2, 0) macro