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Searched refs:RCC_PLLxCFGR5_DIVVAL_MASK (Results 1 – 4 of 4) sorted by relevance

/optee_os/core/include/drivers/
H A Dstm32mp21_rcc.h1196 #define RCC_PLLxCFGR5_DIVVAL_MASK GENMASK_32(3, 0) macro
H A Dstm32mp25_rcc.h1529 #define RCC_PLLxCFGR5_DIVVAL_MASK GENMASK_32(3, 0) macro
/optee_os/core/drivers/clk/
H A Dclk-stm32mp21.c1484 io_clrsetbits32(pllxcfgr5, RCC_PLLxCFGR5_DIVVAL_MASK, in clk_stm32_pll_config_csg()
1485 csg[DIVVAL] & RCC_PLLxCFGR5_DIVVAL_MASK); in clk_stm32_pll_config_csg()
H A Dclk-stm32mp25.c1502 io_clrsetbits32(pllxcfgr5, RCC_PLLxCFGR5_DIVVAL_MASK, in clk_stm32_pll_config_csg()
1503 csg[DIVVAL] & RCC_PLLxCFGR5_DIVVAL_MASK); in clk_stm32_pll_config_csg()