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Searched refs:RCC_PLLNCFGR1_DIVM_MASK (Results 1 – 4 of 4) sorted by relevance

/optee_os/core/include/drivers/
H A Dstm32mp1_rcc.h319 #define RCC_PLLNCFGR1_DIVM_MASK GENMASK_32(21, 16) macro
H A Dstm32mp13_rcc.h1762 #define RCC_PLLNCFGR1_DIVM_MASK GENMASK_32(21, 16) macro
/optee_os/core/drivers/clk/
H A Dclk-stm32mp13.c1101 *value |= (divm << RCC_PLLNCFGR1_DIVM_SHIFT) & RCC_PLLNCFGR1_DIVM_MASK; in clk_stm32_pll_compute_cfgr1()
1160 fracr |= RCC_PLLNCFGR1_DIVM_MASK; in clk_stm32_is_pll_config_on_the_fly()
1727 divm = (cfgr1 & (RCC_PLLNCFGR1_DIVM_MASK)) >> RCC_PLLNCFGR1_DIVM_SHIFT; in clk_stm32_pll_get_rate()
H A Dclk-stm32mp15.c687 divm = (cfgr1 & RCC_PLLNCFGR1_DIVM_MASK) >> RCC_PLLNCFGR1_DIVM_SHIFT; in stm32mp1_pll_get_fvco()