Home
last modified time | relevance | path

Searched refs:RCC_FINDIV0CFGR (Results 1 – 4 of 4) sorted by relevance

/optee_os/core/drivers/clk/
H A Dclk-stm32mp21.c1745 io_clrsetbits32(rcc_base + RCC_FINDIV0CFGR + (0x4 * channel), in flexclkgen_config_channel()
2292 findiv = io_read32(rcc_base + RCC_FINDIV0CFGR + (0x4 * channel)) & in clk_stm32_flexgen_get_rate()
2400 io_clrsetbits32(rcc_base + RCC_FINDIV0CFGR + (0x4 * channel), in clk_stm32_flexgen_set_rate()
2442 io_setbits32(rcc_base + RCC_FINDIV0CFGR + (0x4 * channel), in clk_stm32_flexgen_enable()
2455 io_clrbits32(rcc_base + RCC_FINDIV0CFGR + (0x4 * channel), in clk_stm32_flexgen_disable()
H A Dclk-stm32mp25.c1749 io_clrsetbits32(rcc_base + RCC_FINDIV0CFGR + (0x4 * channel), in flexclkgen_config_channel()
2322 findiv = io_read32(rcc_base + RCC_FINDIV0CFGR + (0x4 * channel)) & in clk_stm32_flexgen_get_rate()
2425 io_clrsetbits32(rcc_base + RCC_FINDIV0CFGR + (0x4 * channel), in clk_stm32_flexgen_set_rate()
2464 io_setbits32(rcc_base + RCC_FINDIV0CFGR + (0x4 * channel), in clk_stm32_flexgen_enable()
2476 io_clrbits32(rcc_base + RCC_FINDIV0CFGR + (0x4 * channel), in clk_stm32_flexgen_disable()
/optee_os/core/include/drivers/
H A Dstm32mp21_rcc.h541 #define RCC_FINDIV0CFGR U(0x1224) macro
H A Dstm32mp25_rcc.h602 #define RCC_FINDIV0CFGR U(0x1224) macro