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Searched refs:MUX_MUXSEL7 (Results 1 – 7 of 7) sorted by relevance

/optee_os/core/arch/arm/dts/
H A Dstm32mp257f-dk-ca35tdcid-rcc.dtsi145 src = <MUX_CFG(MUX_MUXSEL7, MUXSEL_HSE)>;
150 src = <MUX_CFG(MUX_MUXSEL7, MUXSEL_HSE)>;
H A Dstm32mp257f-ev1-ca35tdcid-rcc.dtsi145 src = <MUX_CFG(MUX_MUXSEL7, MUXSEL_HSE)>;
150 src = <MUX_CFG(MUX_MUXSEL7, MUXSEL_HSE)>;
H A Dstm32mp235f-dk-ca35tdcid-rcc.dtsi138 src = <MUX_CFG(MUX_MUXSEL7, MUXSEL_HSE)>;
/optee_os/core/include/dt-bindings/clock/
H A Dstm32mp21-clksrc.h72 #define MUX_MUXSEL7 7 macro
H A Dstm32mp25-clksrc.h98 #define MUX_MUXSEL7 7 macro
/optee_os/core/drivers/clk/
H A Dclk-stm32mp25.c617 _MUX_CFG(MUX_MUXSEL7, RCC_MUXSELCFGR, 28, 2, MUX_NO_RDY),
1016 CLK_PLL_CFG(PLL3_ID, GATE_PLL3, MUX_MUXSEL7, RCC_PLL3CFGR1),
2651 static STM32_PLL3(ck_pll3, 0, RCC_PLL3CFGR1, GATE_PLL3, MUX_MUXSEL7);
H A Dclk-stm32mp21.c582 _MUX_CFG(MUX_MUXSEL7, RCC_MUXSELCFGR, 28, 2, MUX_NO_RDY),