Searched refs:target_itr (Results 1 – 12 of 12) sorted by relevance
452 itr = rc->target_itr; in iavf_update_itr()466 (q_vector->tx.target_itr & IAVF_ITR_ADAPTIVE_LATENCY)) { in iavf_update_itr()476 if (rc->target_itr == IAVF_ITR_ADAPTIVE_MAX_USECS && in iavf_update_itr()477 (q_vector->rx.target_itr & IAVF_ITR_MASK) == in iavf_update_itr()484 rc->target_itr &= ~IAVF_ITR_ADAPTIVE_LATENCY; in iavf_update_itr()496 itr = rc->target_itr + IAVF_ITR_ADAPTIVE_MIN_INC; in iavf_update_itr()602 rc->target_itr = itr; in iavf_update_itr()1658 if (q_vector->rx.target_itr < q_vector->rx.current_itr) { in iavf_update_enable_itr()1661 q_vector->rx.target_itr); in iavf_update_enable_itr()1662 q_vector->rx.current_itr = q_vector->rx.target_itr; in iavf_update_enable_itr()[all …]
781 q_vector->rx.target_itr = ITR_TO_REG(rx_ring->itr_setting); in iavf_set_itr_per_queue()784 q_vector->tx.target_itr = ITR_TO_REG(tx_ring->itr_setting); in iavf_set_itr_per_queue()
420 u16 target_itr; /* target ITR setting for ring(s) */ member
328 q_vector->rx.target_itr = ITR_TO_REG(rx_ring->itr_setting); in iavf_map_vector_to_rxq()332 q_vector->rx.current_itr = q_vector->rx.target_itr; in iavf_map_vector_to_rxq()354 q_vector->tx.target_itr = ITR_TO_REG(tx_ring->itr_setting); in iavf_map_vector_to_txq()357 q_vector->tx.target_itr >> 1); in iavf_map_vector_to_txq()358 q_vector->tx.current_itr = q_vector->tx.target_itr; in iavf_map_vector_to_txq()
1349 itr = rc->target_itr; in ice_update_itr()1381 (q_vector->tx.target_itr & ICE_ITR_ADAPTIVE_LATENCY)) { in ice_update_itr()1391 if (rc->target_itr == ICE_ITR_ADAPTIVE_MAX_USECS && in ice_update_itr()1392 (q_vector->rx.target_itr & ICE_ITR_MASK) == in ice_update_itr()1399 rc->target_itr &= ~ICE_ITR_ADAPTIVE_LATENCY; in ice_update_itr()1411 itr = rc->target_itr + ICE_ITR_ADAPTIVE_MIN_INC; in ice_update_itr()1459 rc->target_itr = itr; in ice_update_itr()1517 rx->target_itr = rx->itr_setting; in ice_update_ena_itr()1538 if (rx->target_itr < rx->current_itr) { in ice_update_ena_itr()1540 itr_val = ice_buildreg_itr(rx->itr_idx, rx->target_itr); in ice_update_ena_itr()[all …]
703 rc->target_itr = ITR_TO_REG(rc->itr_setting); in ice_cfg_itr()705 rc->current_itr = rc->target_itr; in ice_cfg_itr()713 rc->target_itr = ITR_TO_REG(rc->itr_setting); in ice_cfg_itr()715 rc->current_itr = rc->target_itr; in ice_cfg_itr()
341 u16 target_itr; /* value in usecs divided by the hw->itr_gran */ member
3695 rc->target_itr = ITR_REG_ALIGN(rc->itr_setting); in ice_set_rc_coalesce()
1040 itr = rc->target_itr; in i40e_update_itr()1054 (q_vector->tx.target_itr & I40E_ITR_ADAPTIVE_LATENCY)) { in i40e_update_itr()1064 if (rc->target_itr == I40E_ITR_ADAPTIVE_MAX_USECS && in i40e_update_itr()1065 (q_vector->rx.target_itr & I40E_ITR_MASK) == in i40e_update_itr()1072 rc->target_itr &= ~I40E_ITR_ADAPTIVE_LATENCY; in i40e_update_itr()1084 itr = rc->target_itr + I40E_ITR_ADAPTIVE_MIN_INC; in i40e_update_itr()1190 rc->target_itr = itr; in i40e_update_itr()2537 if (q_vector->rx.target_itr < q_vector->rx.current_itr) { in i40e_update_enable_itr()2540 q_vector->rx.target_itr); in i40e_update_enable_itr()2541 q_vector->rx.current_itr = q_vector->rx.target_itr; in i40e_update_enable_itr()[all …]
431 u16 target_itr; /* target ITR setting for ring(s) */ member
3685 q_vector->rx.target_itr = in i40e_vsi_configure_msix()3688 q_vector->rx.target_itr >> 1); in i40e_vsi_configure_msix()3689 q_vector->rx.current_itr = q_vector->rx.target_itr; in i40e_vsi_configure_msix()3692 q_vector->tx.target_itr = in i40e_vsi_configure_msix()3695 q_vector->tx.target_itr >> 1); in i40e_vsi_configure_msix()3696 q_vector->tx.current_itr = q_vector->tx.target_itr; in i40e_vsi_configure_msix()3799 q_vector->rx.target_itr = ITR_TO_REG(vsi->rx_rings[0]->itr_setting); in i40e_configure_msi_and_legacy()3800 wr32(hw, I40E_PFINT_ITR0(I40E_RX_ITR), q_vector->rx.target_itr >> 1); in i40e_configure_msi_and_legacy()3801 q_vector->rx.current_itr = q_vector->rx.target_itr; in i40e_configure_msi_and_legacy()3803 q_vector->tx.target_itr = ITR_TO_REG(vsi->tx_rings[0]->itr_setting); in i40e_configure_msi_and_legacy()[all …]
2887 q_vector->rx.target_itr = ITR_TO_REG(rx_ring->itr_setting); in i40e_set_itr_per_queue()2890 q_vector->tx.target_itr = ITR_TO_REG(tx_ring->itr_setting); in i40e_set_itr_per_queue()