Searched refs:sysclk_sel (Results 1 – 6 of 6) sorted by relevance
97 u32 sysclk_sel; in get_mcu_main_clk() local100 sysclk_sel = readl(CGM_SC_SS(MC_CGM1_BASE_ADDR)) & MC_CGM_SC_SEL_MASK; in get_mcu_main_clk()101 sysclk_sel >>= MC_CGM_SC_SEL_OFFSET; in get_mcu_main_clk()108 switch (sysclk_sel) { in get_mcu_main_clk()132 u32 sysclk_sel; in get_sys_clk() local146 sysclk_sel = readl(CGM_SC_SS(MC_CGM0_BASE_ADDR)) & MC_CGM_SC_SEL_MASK; in get_sys_clk()147 sysclk_sel >>= MC_CGM_SC_SEL_OFFSET; in get_sys_clk()155 switch (sysclk_sel) { in get_sys_clk()
43 u32 sysclk_sel, pll_pfd_sel = 0; in get_mcu_main_clk() local47 sysclk_sel = ccm_ccsr & CCM_CCSR_SYS_CLK_SEL_MASK; in get_mcu_main_clk()48 sysclk_sel >>= CCM_CCSR_SYS_CLK_SEL_OFFSET; in get_mcu_main_clk()55 switch (sysclk_sel) { in get_mcu_main_clk()
22 u8 sysclk_sel; /* 0x8 - */ member
111 printf("sysclk_sel = %x\n", CPLD_READ(sysclk_sel)); in cpld_dump_regs()
23 u8 sysclk_sel; /* 0x8 - System clock POR Register */ member
104 printf("sysclk_sel = %x\n", CPLD_READ(sysclk_sel)); in cpld_dump_regs()