1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright 2015 Freescale Semiconductor 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #ifndef __CPLD_H__ 8*4882a593Smuzhiyun #define __CPLD_H__ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun /* 11*4882a593Smuzhiyun * CPLD register set of LS1043ARDB board-specific. 12*4882a593Smuzhiyun */ 13*4882a593Smuzhiyun struct cpld_data { 14*4882a593Smuzhiyun u8 cpld_ver; /* 0x0 - CPLD Major Revision Register */ 15*4882a593Smuzhiyun u8 cpld_ver_sub; /* 0x1 - CPLD Minor Revision Register */ 16*4882a593Smuzhiyun u8 pcba_ver; /* 0x2 - PCBA Revision Register */ 17*4882a593Smuzhiyun u8 system_rst; /* 0x3 - system reset register */ 18*4882a593Smuzhiyun u8 soft_mux_on; /* 0x4 - Switch Control Enable Register */ 19*4882a593Smuzhiyun u8 cfg_rcw_src1; /* 0x5 - Reset config word 1 */ 20*4882a593Smuzhiyun u8 cfg_rcw_src2; /* 0x6 - Reset config word 1 */ 21*4882a593Smuzhiyun u8 vbank; /* 0x7 - Flash bank selection Control */ 22*4882a593Smuzhiyun u8 sysclk_sel; /* 0x8 - */ 23*4882a593Smuzhiyun u8 uart_sel; /* 0x9 - */ 24*4882a593Smuzhiyun u8 sd1refclk_sel; /* 0xA - */ 25*4882a593Smuzhiyun u8 tdmclk_mux_sel; /* 0xB - */ 26*4882a593Smuzhiyun u8 sdhc_spics_sel; /* 0xC - */ 27*4882a593Smuzhiyun u8 status_led; /* 0xD - */ 28*4882a593Smuzhiyun u8 global_rst; /* 0xE - */ 29*4882a593Smuzhiyun }; 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun u8 cpld_read(unsigned int reg); 32*4882a593Smuzhiyun void cpld_write(unsigned int reg, u8 value); 33*4882a593Smuzhiyun void cpld_rev_bit(unsigned char *value); 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun #define CPLD_READ(reg) cpld_read(offsetof(struct cpld_data, reg)) 36*4882a593Smuzhiyun #define CPLD_WRITE(reg, value) \ 37*4882a593Smuzhiyun cpld_write(offsetof(struct cpld_data, reg), value) 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun /* CPLD on IFC */ 40*4882a593Smuzhiyun #define CPLD_SW_MUX_BANK_SEL 0x40 41*4882a593Smuzhiyun #define CPLD_BANK_SEL_MASK 0x07 42*4882a593Smuzhiyun #define CPLD_BANK_SEL_ALTBANK 0x04 43*4882a593Smuzhiyun #define CPLD_CFG_RCW_SRC_NOR 0x025 44*4882a593Smuzhiyun #define CPLD_CFG_RCW_SRC_NAND 0x106 45*4882a593Smuzhiyun #define CPLD_CFG_RCW_SRC_SD 0x040 46*4882a593Smuzhiyun #endif 47