1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright 2016 Freescale Semiconductor 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #ifndef __CPLD_H__ 8*4882a593Smuzhiyun #define __CPLD_H__ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun /* 11*4882a593Smuzhiyun * CPLD register set of LS1046ARDB board-specific. 12*4882a593Smuzhiyun * CPLD Revision: V2.1 13*4882a593Smuzhiyun */ 14*4882a593Smuzhiyun struct cpld_data { 15*4882a593Smuzhiyun u8 cpld_ver; /* 0x0 - CPLD Major Revision Register */ 16*4882a593Smuzhiyun u8 cpld_ver_sub; /* 0x1 - CPLD Minor Revision Register */ 17*4882a593Smuzhiyun u8 pcba_ver; /* 0x2 - PCBA Revision Register */ 18*4882a593Smuzhiyun u8 system_rst; /* 0x3 - system reset register */ 19*4882a593Smuzhiyun u8 soft_mux_on; /* 0x4 - Switch Control Enable Register */ 20*4882a593Smuzhiyun u8 cfg_rcw_src1; /* 0x5 - RCW Source Location POR Regsiter 1 */ 21*4882a593Smuzhiyun u8 cfg_rcw_src2; /* 0x6 - RCW Source Location POR Regsiter 2 */ 22*4882a593Smuzhiyun u8 vbank; /* 0x7 - QSPI Flash Bank Setting Register */ 23*4882a593Smuzhiyun u8 sysclk_sel; /* 0x8 - System clock POR Register */ 24*4882a593Smuzhiyun u8 uart_sel; /* 0x9 - UART1 Connection Control Register */ 25*4882a593Smuzhiyun u8 sd1refclk_sel; /* 0xA - */ 26*4882a593Smuzhiyun u8 rgmii_1588_sel; /* 0xB - */ 27*4882a593Smuzhiyun u8 reg_1588_clk_sel; /* 0xC - */ 28*4882a593Smuzhiyun u8 status_led; /* 0xD - */ 29*4882a593Smuzhiyun u8 global_rst; /* 0xE - */ 30*4882a593Smuzhiyun u8 sd_emmc; /* 0xF - SD/EMMC Interface Control Regsiter */ 31*4882a593Smuzhiyun u8 vdd_en; /* 0x10 - VDD Voltage Control Enable Register */ 32*4882a593Smuzhiyun u8 vdd_sel; /* 0x11 - VDD Voltage Control Register */ 33*4882a593Smuzhiyun }; 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun u8 cpld_read(unsigned int reg); 36*4882a593Smuzhiyun void cpld_write(unsigned int reg, u8 value); 37*4882a593Smuzhiyun void cpld_rev_bit(unsigned char *value); 38*4882a593Smuzhiyun void cpld_select_core_volt(bool en_0v9); 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun #define CPLD_READ(reg) cpld_read(offsetof(struct cpld_data, reg)) 41*4882a593Smuzhiyun #define CPLD_WRITE(reg, value) \ 42*4882a593Smuzhiyun cpld_write(offsetof(struct cpld_data, reg), value) 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun /* CPLD on IFC */ 45*4882a593Smuzhiyun #define CPLD_SW_MUX_BANK_SEL 0x40 46*4882a593Smuzhiyun #define CPLD_BANK_SEL_MASK 0x07 47*4882a593Smuzhiyun #define CPLD_BANK_SEL_ALTBANK 0x04 48*4882a593Smuzhiyun #define CPLD_CFG_RCW_SRC_QSPI 0x044 49*4882a593Smuzhiyun #define CPLD_CFG_RCW_SRC_SD 0x040 50*4882a593Smuzhiyun #endif 51