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Searched refs:src_clk_div (Results 1 – 17 of 17) sorted by relevance

/OK3568_Linux_fs/u-boot/drivers/clk/rockchip/
H A Dclk_rk1808.c137 int src_clk_div; in rk1808_i2c_set_clk() local
139 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, hz); in rk1808_i2c_set_clk()
140 assert(src_clk_div - 1 < 127); in rk1808_i2c_set_clk()
146 (src_clk_div - 1) << CLK_I2C0_DIV_CON_SHIFT | in rk1808_i2c_set_clk()
152 (src_clk_div - 1) << CLK_I2C1_DIV_CON_SHIFT | in rk1808_i2c_set_clk()
158 (src_clk_div - 1) << CLK_I2C2_DIV_CON_SHIFT | in rk1808_i2c_set_clk()
164 (src_clk_div - 1) << CLK_I2C3_DIV_CON_SHIFT | in rk1808_i2c_set_clk()
170 (src_clk_div - 1) << CLK_I2C4_DIV_CON_SHIFT | in rk1808_i2c_set_clk()
176 (src_clk_div - 1) << CLK_I2C5_DIV_CON_SHIFT | in rk1808_i2c_set_clk()
225 int src_clk_div; in rk1808_mmc_set_clk() local
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H A Dclk_rv1126.c239 int src_clk_div; in rv1126_i2c_set_pmuclk() local
241 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, rate); in rv1126_i2c_set_pmuclk()
242 assert(src_clk_div - 1 <= 127); in rv1126_i2c_set_pmuclk()
247 (src_clk_div - 1) << CLK_I2C0_DIV_SHIFT); in rv1126_i2c_set_pmuclk()
251 (src_clk_div - 1) << CLK_I2C2_DIV_SHIFT); in rv1126_i2c_set_pmuclk()
292 int src_clk_div; in rv1126_pwm_set_pmuclk() local
303 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, rate); in rv1126_pwm_set_pmuclk()
304 assert(src_clk_div - 1 <= 127); in rv1126_pwm_set_pmuclk()
307 (src_clk_div - 1) << CLK_PWM0_DIV_SHIFT); in rv1126_pwm_set_pmuclk()
321 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, rate); in rv1126_pwm_set_pmuclk()
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H A Dclk_rk3328.c201 int src_clk_div; in rk3328_i2c_set_clk() local
203 src_clk_div = priv->gpll_hz / hz; in rk3328_i2c_set_clk()
204 assert(src_clk_div - 1 < 127); in rk3328_i2c_set_clk()
211 (src_clk_div - 1) << CLK_I2C0_DIV_CON_SHIFT | in rk3328_i2c_set_clk()
218 (src_clk_div - 1) << CLK_I2C1_DIV_CON_SHIFT | in rk3328_i2c_set_clk()
225 (src_clk_div - 1) << CLK_I2C2_DIV_CON_SHIFT | in rk3328_i2c_set_clk()
232 (src_clk_div - 1) << CLK_I2C3_DIV_CON_SHIFT | in rk3328_i2c_set_clk()
240 return DIV_TO_RATE(priv->gpll_hz, src_clk_div); in rk3328_i2c_set_clk()
348 int src_clk_div; in rk3328_mmc_set_clk() local
365 src_clk_div = DIV_ROUND_UP(priv->gpll_hz / 2, set_rate); in rk3328_mmc_set_clk()
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H A Dclk_rv1108.c202 int src_clk_div; in rv1108_saradc_set_clk() local
204 src_clk_div = DIV_ROUND_UP(OSC_HZ, hz) - 1; in rv1108_saradc_set_clk()
205 assert(src_clk_div < 128); in rv1108_saradc_set_clk()
209 src_clk_div << CLK_SARADC_DIV_CON_SHIFT); in rv1108_saradc_set_clk()
227 int src_clk_div; in rv1108_aclk_vio1_set_clk() local
229 src_clk_div = DIV_ROUND_UP(GPLL_HZ, hz) - 1; in rv1108_aclk_vio1_set_clk()
230 assert(src_clk_div < 32); in rv1108_aclk_vio1_set_clk()
234 (src_clk_div << ACLK_VIO1_CLK_DIV_SHIFT) | in rv1108_aclk_vio1_set_clk()
253 int src_clk_div; in rv1108_aclk_vio0_set_clk() local
255 src_clk_div = DIV_ROUND_UP(GPLL_HZ, hz) - 1; in rv1108_aclk_vio0_set_clk()
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H A Dclk_rk3128.c181 int src_clk_div; in rockchip_mmc_set_clk() local
185 src_clk_div = DIV_ROUND_UP(priv->gpll_hz / 2, freq); in rockchip_mmc_set_clk()
187 if (src_clk_div > 128) { in rockchip_mmc_set_clk()
188 src_clk_div = DIV_ROUND_UP(OSC_HZ / 2, freq); in rockchip_mmc_set_clk()
200 (src_clk_div - 1) << EMMC_DIV_SHIFT); in rockchip_mmc_set_clk()
207 (src_clk_div - 1) << MMC0_DIV_SHIFT); in rockchip_mmc_set_clk()
214 (src_clk_div - 1) << SDIO_DIV_SHIFT); in rockchip_mmc_set_clk()
262 int src_clk_div; in rk3128_peri_set_clk() local
266 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, hz); in rk3128_peri_set_clk()
267 assert(src_clk_div - 1 < 32); in rk3128_peri_set_clk()
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H A Dclk_px30.c330 int src_clk_div; in px30_i2c_set_clk() local
332 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, hz); in px30_i2c_set_clk()
333 assert(src_clk_div - 1 <= 127); in px30_i2c_set_clk()
340 (src_clk_div - 1) << CLK_I2C0_DIV_CON_SHIFT | in px30_i2c_set_clk()
347 (src_clk_div - 1) << CLK_I2C1_DIV_CON_SHIFT | in px30_i2c_set_clk()
354 (src_clk_div - 1) << CLK_I2C2_DIV_CON_SHIFT | in px30_i2c_set_clk()
361 (src_clk_div - 1) << CLK_I2C3_DIV_CON_SHIFT | in px30_i2c_set_clk()
534 int src_clk_div; in px30_nandc_set_clk() local
538 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, set_rate); in px30_nandc_set_clk()
539 assert(src_clk_div - 1 <= 31); in px30_nandc_set_clk()
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H A Dclk_rk3308.c230 u32 src_clk_div, con_id; in rk3308_i2c_set_clk() local
232 src_clk_div = DIV_ROUND_UP(priv->dpll_hz, hz); in rk3308_i2c_set_clk()
233 assert(src_clk_div - 1 <= 127); in rk3308_i2c_set_clk()
255 (src_clk_div - 1) << CLK_I2C_DIV_CON_SHIFT); in rk3308_i2c_set_clk()
340 int src_clk_div; in rk3308_mmc_set_clk() local
359 src_clk_div = DIV_ROUND_UP(priv->vpll0_hz / 2, set_rate); in rk3308_mmc_set_clk()
361 if (src_clk_div > 127) { in rk3308_mmc_set_clk()
363 src_clk_div = DIV_ROUND_UP(OSC_HZ / 2, set_rate); in rk3308_mmc_set_clk()
368 (src_clk_div - 1) << EMMC_DIV_SHIFT); in rk3308_mmc_set_clk()
374 (src_clk_div - 1) << EMMC_DIV_SHIFT); in rk3308_mmc_set_clk()
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H A Dclk_rk322x.c221 int src_clk_div; in rk322x_mmc_set_clk() local
225 src_clk_div = DIV_ROUND_UP(priv->gpll_hz / 2, freq); in rk322x_mmc_set_clk()
227 if (src_clk_div > 128) { in rk322x_mmc_set_clk()
228 src_clk_div = DIV_ROUND_UP(OSC_HZ / 2, freq); in rk322x_mmc_set_clk()
229 assert(src_clk_div - 1 < 128); in rk322x_mmc_set_clk()
244 (src_clk_div - 1) << EMMC_DIV_SHIFT); in rk322x_mmc_set_clk()
252 (src_clk_div - 1) << MMC0_DIV_SHIFT); in rk322x_mmc_set_clk()
261 (src_clk_div - 1) << SDIO_DIV_SHIFT); in rk322x_mmc_set_clk()
307 int src_clk_div; in rk322x_bus_set_clk() local
315 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, hz); in rk322x_bus_set_clk()
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H A Dclk_rk3399.c623 int src_clk_div; in rk3399_i2c_set_clk() local
626 src_clk_div = GPLL_HZ / hz; in rk3399_i2c_set_clk()
627 assert(src_clk_div - 1 <= 127); in rk3399_i2c_set_clk()
632 I2C_CLK_REG_VALUE(1, src_clk_div)); in rk3399_i2c_set_clk()
636 I2C_CLK_REG_VALUE(2, src_clk_div)); in rk3399_i2c_set_clk()
640 I2C_CLK_REG_VALUE(3, src_clk_div)); in rk3399_i2c_set_clk()
644 I2C_CLK_REG_VALUE(5, src_clk_div)); in rk3399_i2c_set_clk()
648 I2C_CLK_REG_VALUE(6, src_clk_div)); in rk3399_i2c_set_clk()
652 I2C_CLK_REG_VALUE(7, src_clk_div)); in rk3399_i2c_set_clk()
723 int src_clk_div; in rk3399_spi_set_clk() local
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H A Dclk_rk3036.c273 int src_clk_div; in rockchip_mmc_set_clk() local
279 src_clk_div = DIV_ROUND_UP(clk_general_rate / 2, freq); in rockchip_mmc_set_clk()
281 if (src_clk_div > 128) { in rockchip_mmc_set_clk()
282 src_clk_div = DIV_ROUND_UP(OSC_HZ / 2, freq); in rockchip_mmc_set_clk()
283 assert(src_clk_div - 1 < 128); in rockchip_mmc_set_clk()
295 (src_clk_div - 1) << EMMC_DIV_SHIFT); in rockchip_mmc_set_clk()
302 (src_clk_div - 1) << MMC0_DIV_SHIFT); in rockchip_mmc_set_clk()
355 int src_clk_div; in rockchip_dclk_lcdc_set_clk() local
357 src_clk_div = DIV_ROUND_UP(clk_general_rate, freq); in rockchip_dclk_lcdc_set_clk()
358 assert(src_clk_div - 1 <= 255); in rockchip_dclk_lcdc_set_clk()
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H A Dclk_rk3368.c539 int src_clk_div; in rk3368_spi_set_clk() local
541 src_clk_div = DIV_ROUND_UP(GPLL_HZ, hz); in rk3368_spi_set_clk()
542 assert(src_clk_div < 127); in rk3368_spi_set_clk()
557 ((src_clk_div << spiclk->div_shift) | in rk3368_spi_set_clk()
576 int src_clk_div; in rk3368_saradc_set_clk() local
578 src_clk_div = DIV_ROUND_UP(OSC_HZ, hz) - 1; in rk3368_saradc_set_clk()
579 assert(src_clk_div < 128); in rk3368_saradc_set_clk()
583 src_clk_div << CLK_SARADC_DIV_CON_SHIFT); in rk3368_saradc_set_clk()
622 int src_clk_div; in rk3368_bus_set_clk() local
630 src_clk_div = DIV_ROUND_UP(rkclk_pll_get_rate(cru, GPLL), hz); in rk3368_bus_set_clk()
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H A Dclk_rk3188.c310 int src_clk_div; in rockchip_mmc_set_clk() local
314 src_clk_div = DIV_ROUND_UP(gclk_rate / 2, freq) - 1; in rockchip_mmc_set_clk()
315 assert(src_clk_div <= 0x3f); in rockchip_mmc_set_clk()
322 src_clk_div << EMMC_DIV_SHIFT); in rockchip_mmc_set_clk()
328 src_clk_div << MMC0_DIV_SHIFT); in rockchip_mmc_set_clk()
334 src_clk_div << SDIO_DIV_SHIFT); in rockchip_mmc_set_clk()
368 int src_clk_div = DIV_ROUND_UP(gclk_rate, freq) - 1; in rockchip_spi_set_clk() local
370 assert(src_clk_div < 128); in rockchip_spi_set_clk()
373 assert(src_clk_div <= SPI0_DIV_MASK); in rockchip_spi_set_clk()
376 src_clk_div << SPI0_DIV_SHIFT); in rockchip_spi_set_clk()
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H A Dclk_rk3288.c752 int src_clk_div; in rockchip_mmc_set_clk() local
757 src_clk_div = DIV_ROUND_UP(gclk_rate / 2, freq); in rockchip_mmc_set_clk()
759 if (src_clk_div > 0x3f) { in rockchip_mmc_set_clk()
760 src_clk_div = DIV_ROUND_UP(OSC_HZ / 2, freq); in rockchip_mmc_set_clk()
761 assert(src_clk_div < 0x40); in rockchip_mmc_set_clk()
776 (src_clk_div - 1) << EMMC_DIV_SHIFT); in rockchip_mmc_set_clk()
783 (src_clk_div - 1) << MMC0_DIV_SHIFT); in rockchip_mmc_set_clk()
790 (src_clk_div - 1) << SDIO0_DIV_SHIFT); in rockchip_mmc_set_clk()
832 int src_clk_div; in rockchip_spi_set_clk() local
835 src_clk_div = DIV_ROUND_UP(gclk_rate, freq) - 1; in rockchip_spi_set_clk()
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H A Dclk_rk3066.c309 int src_clk_div; in rockchip_mmc_set_clk() local
312 src_clk_div = RATE_TO_DIV(gclk_rate, freq); in rockchip_mmc_set_clk()
313 if (src_clk_div > 0x3f) in rockchip_mmc_set_clk()
314 src_clk_div = 0x3f; in rockchip_mmc_set_clk()
320 src_clk_div << EMMC_DIV_SHIFT); in rockchip_mmc_set_clk()
325 src_clk_div << MMC0_DIV_SHIFT); in rockchip_mmc_set_clk()
330 src_clk_div << SDIO_DIV_SHIFT); in rockchip_mmc_set_clk()
364 int src_clk_div = RATE_TO_DIV(gclk_rate, freq); in rockchip_spi_set_clk() local
368 assert(src_clk_div <= SPI0_DIV_MASK >> SPI0_DIV_SHIFT); in rockchip_spi_set_clk()
371 src_clk_div << SPI0_DIV_SHIFT); in rockchip_spi_set_clk()
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H A Dclk_rk3568.c266 int src_clk_div; in rk3568_i2c_set_pmuclk() local
268 src_clk_div = DIV_ROUND_UP(priv->ppll_hz, rate); in rk3568_i2c_set_pmuclk()
269 assert(src_clk_div - 1 <= 127); in rk3568_i2c_set_pmuclk()
274 (src_clk_div - 1) << CLK_I2C0_DIV_SHIFT); in rk3568_i2c_set_pmuclk()
310 int src_clk_div; in rk3568_pwm_set_pmuclk() local
321 src_clk_div = DIV_ROUND_UP(priv->ppll_hz, rate); in rk3568_pwm_set_pmuclk()
322 assert(src_clk_div - 1 <= 127); in rk3568_pwm_set_pmuclk()
326 (src_clk_div - 1) << CLK_PWM0_DIV_SHIFT); in rk3568_pwm_set_pmuclk()
356 int src_clk_div; in rk3568_pmu_set_pmuclk() local
358 src_clk_div = DIV_ROUND_UP(priv->ppll_hz, rate); in rk3568_pmu_set_pmuclk()
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H A Dclk_rv1106.c431 u32 sel, src_clk_div; in rv1106_mmc_set_clk() local
441 src_clk_div = DIV_ROUND_UP(prate, rate); in rv1106_mmc_set_clk()
453 src_clk_div = DIV_ROUND_UP(prate, rate); in rv1106_mmc_set_clk()
458 ((src_clk_div - 1) << in rv1106_mmc_set_clk()
470 src_clk_div = DIV_ROUND_UP(prate, rate); in rv1106_mmc_set_clk()
475 ((src_clk_div - 1) << in rv1106_mmc_set_clk()
493 src_clk_div = DIV_ROUND_UP(prate, rate); in rv1106_mmc_set_clk()
498 ((src_clk_div - 1) << in rv1106_mmc_set_clk()
721 int src_clk_div; in rv1106_adc_set_clk() local
723 src_clk_div = DIV_ROUND_UP(OSC_HZ, rate); in rv1106_adc_set_clk()
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H A Dclk_rk3588.c331 int src_clk, src_clk_div; in rk3588_top_set_clk() local
337 src_clk_div = DIV_ROUND_UP(priv->cpll_hz, rate); in rk3588_top_set_clk()
340 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, rate); in rk3588_top_set_clk()
342 assert(src_clk_div - 1 <= 31); in rk3588_top_set_clk()
348 (src_clk_div - 1) << ACLK_TOP_ROOT_DIV_SHIFT); in rk3588_top_set_clk()
351 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, rate); in rk3588_top_set_clk()
352 assert(src_clk_div - 1 <= 31); in rk3588_top_set_clk()
358 (src_clk_div - 1) << ACLK_LOW_TOP_ROOT_DIV_SHIFT); in rk3588_top_set_clk()
688 int src_clk_div; in rk3588_adc_set_clk() local
693 src_clk_div = DIV_ROUND_UP(OSC_HZ, rate); in rk3588_adc_set_clk()
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