Searched refs:s_RGA2_ALPHA_CTRL1_SW_DST_BLEND_M0 (Results 1 – 3 of 3) sorted by relevance
215 #define s_RGA2_ALPHA_CTRL1_SW_DST_BLEND_M0(x) ( (x&0x3)<<10) macro
746 …reg1 = ((reg1 & (~m_RGA2_ALPHA_CTRL1_SW_DST_BLEND_M0)) | (s_RGA2_ALPHA_CTRL1_SW_DST_BLEND_M0(msg->… in RGA2_set_reg_alpha_info()
389 #define s_RGA2_ALPHA_CTRL1_SW_DST_BLEND_M0(x) ((x & 0x3) << 10) macro