1 /* SPDX-License-Identifier: GPL-2.0 */
2
3 //#include <linux/kernel.h>
4 #include <linux/memory.h>
5 #include <linux/kernel.h>
6 #include <linux/init.h>
7 #include <linux/module.h>
8 #include <linux/platform_device.h>
9 #include <linux/sched.h>
10 #include <linux/mutex.h>
11 #include <linux/err.h>
12 #include <linux/clk.h>
13 #include <asm/delay.h>
14 #include <linux/dma-mapping.h>
15 #include <linux/delay.h>
16 #include <asm/io.h>
17 #include <linux/irq.h>
18 #include <linux/interrupt.h>
19 #include <linux/fs.h>
20 #include <linux/uaccess.h>
21 #include <linux/miscdevice.h>
22 #include <linux/poll.h>
23 #include <linux/delay.h>
24 #include <linux/wait.h>
25 #include <linux/syscalls.h>
26 #include <linux/timer.h>
27 #include <linux/time.h>
28 #include <asm/cacheflush.h>
29 #include <linux/slab.h>
30 #include <linux/fb.h>
31 #include <linux/wakelock.h>
32 #include <linux/version.h>
33
34 #include "rga2_reg_info.h"
35 #include "rga2_type.h"
36 #include "rga2_rop.h"
37 #include "rga2.h"
38
RGA2_reg_get_param(unsigned char * base,struct rga2_req * msg)39 static void RGA2_reg_get_param(unsigned char *base, struct rga2_req *msg)
40 {
41 RK_U32 *bRGA_SRC_INFO;
42 RK_U32 *bRGA_SRC_X_FACTOR;
43 RK_U32 *bRGA_SRC_Y_FACTOR;
44 RK_U32 sw, sh;
45 RK_U32 dw, dh;
46 RK_U32 param_x, param_y;
47 RK_U8 x_flag, y_flag;
48
49 RK_U32 reg;
50
51 bRGA_SRC_INFO = (RK_U32 *)(base + RGA2_SRC_INFO_OFFSET);
52 reg = *bRGA_SRC_INFO;
53
54 bRGA_SRC_X_FACTOR = (RK_U32 *)(base + RGA2_SRC_X_FACTOR_OFFSET);
55 bRGA_SRC_Y_FACTOR = (RK_U32 *)(base + RGA2_SRC_Y_FACTOR_OFFSET);
56
57 x_flag = y_flag = 0;
58
59 if(((msg->rotate_mode & 0x3) == 1) || ((msg->rotate_mode & 0x3) == 3))
60 {
61 dw = msg->dst.act_h;
62 dh = msg->dst.act_w;
63 }
64 else
65 {
66 dw = msg->dst.act_w;
67 dh = msg->dst.act_h;
68 }
69
70 sw = msg->src.act_w;
71 sh = msg->src.act_h;
72
73 if (sw > dw)
74 {
75 x_flag = 1;
76 #if SCALE_DOWN_LARGE
77 param_x = ((dw) << 16) / (sw) + 1;
78 #else
79 param_x = ((dw) << 16) / (sw);
80 #endif
81 *bRGA_SRC_X_FACTOR |= ((param_x & 0xffff) << 0 );
82 }
83 else if (sw < dw)
84 {
85 x_flag = 2;
86 #if 1//SCALE_MINUS1
87 param_x = ((sw - 1) << 16) / (dw - 1);
88 #else
89 param_x = ((sw) << 16) / (dw);
90 #endif
91 *bRGA_SRC_X_FACTOR |= ((param_x & 0xffff) << 16);
92 }
93 else
94 {
95 *bRGA_SRC_X_FACTOR = 0;//((1 << 14) << 16) | (1 << 14);
96 }
97
98 if (sh > dh)
99 {
100 y_flag = 1;
101 #if SCALE_DOWN_LARGE
102 param_y = ((dh) << 16) / (sh) + 1;
103 #else
104 param_y = ((dh) << 16) / (sh);
105 #endif
106 *bRGA_SRC_Y_FACTOR |= ((param_y & 0xffff) << 0 );
107 }
108 else if (sh < dh)
109 {
110 y_flag = 2;
111 #if 1//SCALE_MINUS1
112 param_y = ((sh - 1) << 16) / (dh - 1);
113 #else
114 param_y = ((sh) << 16) / (dh);
115 #endif
116 *bRGA_SRC_Y_FACTOR |= ((param_y & 0xffff) << 16);
117 }
118 else
119 {
120 *bRGA_SRC_Y_FACTOR = 0;//((1 << 14) << 16) | (1 << 14);
121 }
122
123 reg = ((reg & (~m_RGA2_SRC_INFO_SW_SW_SRC_HSCL_MODE)) | (s_RGA2_SRC_INFO_SW_SW_SRC_HSCL_MODE(x_flag)));
124 reg = ((reg & (~m_RGA2_SRC_INFO_SW_SW_SRC_VSCL_MODE)) | (s_RGA2_SRC_INFO_SW_SW_SRC_VSCL_MODE(y_flag)));
125 }
126
RGA2_set_mode_ctrl(u8 * base,struct rga2_req * msg)127 static void RGA2_set_mode_ctrl(u8 *base, struct rga2_req *msg)
128 {
129 RK_U32 *bRGA_MODE_CTL;
130 RK_U32 reg = 0;
131 RK_U32 render_mode = msg->render_mode;
132
133 bRGA_MODE_CTL = (u32 *)(base + RGA2_MODE_CTRL_OFFSET);
134
135 if(msg->render_mode == 4)
136 {
137 render_mode = 3;
138 }
139
140 reg = ((reg & (~m_RGA2_MODE_CTRL_SW_RENDER_MODE)) | (s_RGA2_MODE_CTRL_SW_RENDER_MODE(render_mode)));
141 reg = ((reg & (~m_RGA2_MODE_CTRL_SW_BITBLT_MODE)) | (s_RGA2_MODE_CTRL_SW_BITBLT_MODE(msg->bitblt_mode)));
142 reg = ((reg & (~m_RGA2_MODE_CTRL_SW_CF_ROP4_PAT)) | (s_RGA2_MODE_CTRL_SW_CF_ROP4_PAT(msg->color_fill_mode)));
143 reg = ((reg & (~m_RGA2_MODE_CTRL_SW_ALPHA_ZERO_KET)) | (s_RGA2_MODE_CTRL_SW_ALPHA_ZERO_KET(msg->alpha_zero_key)));
144 reg = ((reg & (~m_RGA2_MODE_CTRL_SW_GRADIENT_SAT)) | (s_RGA2_MODE_CTRL_SW_GRADIENT_SAT(msg->alpha_rop_flag >> 7)));
145 reg = ((reg & (~m_RGA2_MODE_CTRL_SW_INTR_CF_E)) | (s_RGA2_MODE_CTRL_SW_INTR_CF_E(msg->CMD_fin_int_enable)));
146
147 *bRGA_MODE_CTL = reg;
148 }
149
RGA2_set_reg_src_info(RK_U8 * base,struct rga2_req * msg)150 static void RGA2_set_reg_src_info(RK_U8 *base, struct rga2_req *msg)
151 {
152 RK_U32 *bRGA_SRC_INFO;
153 RK_U32 *bRGA_SRC_BASE0, *bRGA_SRC_BASE1, *bRGA_SRC_BASE2;
154 RK_U32 *bRGA_SRC_VIR_INFO;
155 RK_U32 *bRGA_SRC_ACT_INFO;
156 RK_U32 *bRGA_MASK_ADDR;
157 RK_U32 *bRGA_SRC_TR_COLOR0, *bRGA_SRC_TR_COLOR1;
158 RK_U8 src_fmt_yuv400_en = 0;
159
160 RK_U32 reg = 0;
161 RK_U8 src0_format = 0;
162
163 RK_U8 src0_rb_swp = 0;
164 RK_U8 src0_rgb_pack = 0;
165 RK_U8 src0_alpha_swp = 0;
166
167 RK_U8 src0_cbcr_swp = 0;
168 RK_U8 pixel_width = 1;
169 RK_U32 stride = 0;
170 RK_U32 uv_stride = 0;
171 RK_U32 mask_stride = 0;
172 RK_U32 ydiv = 1, xdiv = 2;
173 RK_U8 yuv10 = 0;
174
175 RK_U32 sw, sh;
176 RK_U32 dw, dh;
177 RK_U8 rotate_mode;
178 RK_U8 scale_w_flag, scale_h_flag;
179
180 bRGA_SRC_INFO = (RK_U32 *)(base + RGA2_SRC_INFO_OFFSET);
181
182 bRGA_SRC_BASE0 = (RK_U32 *)(base + RGA2_SRC_BASE0_OFFSET);
183 bRGA_SRC_BASE1 = (RK_U32 *)(base + RGA2_SRC_BASE1_OFFSET);
184 bRGA_SRC_BASE2 = (RK_U32 *)(base + RGA2_SRC_BASE2_OFFSET);
185
186 bRGA_SRC_VIR_INFO = (RK_U32 *)(base + RGA2_SRC_VIR_INFO_OFFSET);
187 bRGA_SRC_ACT_INFO = (RK_U32 *)(base + RGA2_SRC_ACT_INFO_OFFSET);
188
189 bRGA_MASK_ADDR = (RK_U32 *)(base + RGA2_MASK_BASE_OFFSET);
190
191 bRGA_SRC_TR_COLOR0 = (RK_U32 *)(base + RGA2_SRC_TR_COLOR0_OFFSET);
192 bRGA_SRC_TR_COLOR1 = (RK_U32 *)(base + RGA2_SRC_TR_COLOR1_OFFSET);
193
194 if (msg->src.format == RGA2_FORMAT_YCbCr_420_SP_10B ||
195 msg->src.format == RGA2_FORMAT_YCrCb_420_SP_10B) {
196 if ((msg->src.act_w == msg->dst.act_w) &&
197 (msg->src.act_h == msg->dst.act_h) &&
198 (msg->rotate_mode == 0))
199 msg->rotate_mode = 1 << 6;
200 }
201
202 {
203 rotate_mode = msg->rotate_mode & 0x3;
204
205 sw = msg->src.act_w;
206 sh = msg->src.act_h;
207
208 if((rotate_mode == 1) | (rotate_mode == 3))
209 {
210 dw = msg->dst.act_h;
211 dh = msg->dst.act_w;
212 }
213 else
214 {
215 dw = msg->dst.act_w;
216 dh = msg->dst.act_h;
217 }
218
219 if(sw > dw)
220 scale_w_flag = 1;
221 else if (sw < dw)
222 scale_w_flag = 2;
223 else {
224 scale_w_flag = 0;
225 if(msg->rotate_mode >> 6)
226 scale_w_flag = 3;
227 }
228
229 if(sh > dh)
230 scale_h_flag = 1;
231 else if (sh < dh)
232 scale_h_flag = 2;
233 else {
234 scale_h_flag = 0;
235 if(msg->rotate_mode >> 6)
236 scale_h_flag = 3;
237 }
238 }
239
240 switch (msg->src.format)
241 {
242 case RGA2_FORMAT_RGBA_8888 : src0_format = 0x0; pixel_width = 4; break;
243 case RGA2_FORMAT_BGRA_8888 : src0_format = 0x0; src0_rb_swp = 0x1; pixel_width = 4; break;
244 case RGA2_FORMAT_RGBX_8888 : src0_format = 0x1; pixel_width = 4; msg->src_trans_mode &= 0x07; break;
245 case RGA2_FORMAT_BGRX_8888 : src0_format = 0x1; src0_rb_swp = 0x1; pixel_width = 4; msg->src_trans_mode &= 0x07; break;
246 case RGA2_FORMAT_RGB_888 : src0_format = 0x2; src0_rgb_pack = 1; pixel_width = 3; msg->src_trans_mode &= 0x07; break;
247 case RGA2_FORMAT_BGR_888 : src0_format = 0x2; src0_rgb_pack = 1; src0_rb_swp = 1; pixel_width = 3; msg->src_trans_mode &= 0x07; break;
248 case RGA2_FORMAT_RGB_565 : src0_format = 0x4; pixel_width = 2; msg->src_trans_mode &= 0x07; break;
249 case RGA2_FORMAT_RGBA_5551 : src0_format = 0x5; pixel_width = 2; src0_rb_swp = 0x1; break;
250 case RGA2_FORMAT_RGBA_4444 : src0_format = 0x6; pixel_width = 2; src0_rb_swp = 0x1; break;
251 case RGA2_FORMAT_BGR_565 : src0_format = 0x4; pixel_width = 2; msg->src_trans_mode &= 0x07; src0_rb_swp = 0x1; break;
252 case RGA2_FORMAT_BGRA_5551 : src0_format = 0x5; pixel_width = 2; break;
253 case RGA2_FORMAT_BGRA_4444 : src0_format = 0x6; pixel_width = 2; break;
254
255 /* ARGB */
256 /* In colorkey mode, xrgb/xbgr does not need to enable the alpha channel */
257 case RGA2_FORMAT_ARGB_8888 : src0_format = 0x0; pixel_width = 4; src0_alpha_swp = 1; break;
258 case RGA2_FORMAT_ABGR_8888 : src0_format = 0x0; pixel_width = 4; src0_alpha_swp = 1; src0_rb_swp = 0x1; break;
259 case RGA2_FORMAT_XRGB_8888 : src0_format = 0x1; pixel_width = 4; src0_alpha_swp = 1; msg->src_trans_mode &= 0x07; break;
260 case RGA2_FORMAT_XBGR_8888 : src0_format = 0x1; pixel_width = 4; src0_alpha_swp = 1; src0_rb_swp = 0x1; msg->src_trans_mode &= 0x07; break;
261 case RGA2_FORMAT_ARGB_5551 : src0_format = 0x5; pixel_width = 2; src0_alpha_swp = 1; break;
262 case RGA2_FORMAT_ABGR_5551 : src0_format = 0x5; pixel_width = 2; src0_alpha_swp = 1; src0_rb_swp = 0x1; break;
263 case RGA2_FORMAT_ARGB_4444 : src0_format = 0x6; pixel_width = 2; src0_alpha_swp = 1; break;
264 case RGA2_FORMAT_ABGR_4444 : src0_format = 0x6; pixel_width = 2; src0_alpha_swp = 1; src0_rb_swp = 0x1; break;
265
266 case RGA2_FORMAT_YVYU_422 : src0_format = 0x7; pixel_width = 2; src0_cbcr_swp = 1; src0_rb_swp = 0x1; break;//rbswap=ycswap
267 case RGA2_FORMAT_VYUY_422 : src0_format = 0x7; pixel_width = 2; src0_cbcr_swp = 1; src0_rb_swp = 0x0; break;
268 case RGA2_FORMAT_YUYV_422 : src0_format = 0x7; pixel_width = 2; src0_cbcr_swp = 0; src0_rb_swp = 0x1; break;
269 case RGA2_FORMAT_UYVY_422 : src0_format = 0x7; pixel_width = 2; src0_cbcr_swp = 0; src0_rb_swp = 0x0; break;
270
271 case RGA2_FORMAT_YCbCr_422_SP : src0_format = 0x8; xdiv = 1; ydiv = 1; break;
272 case RGA2_FORMAT_YCbCr_422_P : src0_format = 0x9; xdiv = 2; ydiv = 1; break;
273 case RGA2_FORMAT_YCbCr_420_SP : src0_format = 0xa; xdiv = 1; ydiv = 2; break;
274 case RGA2_FORMAT_YCbCr_420_P : src0_format = 0xb; xdiv = 2; ydiv = 2; break;
275 case RGA2_FORMAT_YCrCb_422_SP : src0_format = 0x8; xdiv = 1; ydiv = 1; src0_cbcr_swp = 1; break;
276 case RGA2_FORMAT_YCrCb_422_P : src0_format = 0x9; xdiv = 2; ydiv = 1; src0_cbcr_swp = 1; break;
277 case RGA2_FORMAT_YCrCb_420_SP : src0_format = 0xa; xdiv = 1; ydiv = 2; src0_cbcr_swp = 1; break;
278 case RGA2_FORMAT_YCrCb_420_P : src0_format = 0xb; xdiv = 2; ydiv = 2; src0_cbcr_swp = 1; break;
279
280 case RGA2_FORMAT_YCbCr_420_SP_10B : src0_format = 0xa; xdiv = 1; ydiv = 2; yuv10 = 1; break;
281 case RGA2_FORMAT_YCrCb_420_SP_10B : src0_format = 0xa; xdiv = 1; ydiv = 2; src0_cbcr_swp = 1; yuv10 = 1; break;
282 case RGA2_FORMAT_YCbCr_422_SP_10B : src0_format = 0x8; xdiv = 1; ydiv = 1; yuv10 = 1; break;
283 case RGA2_FORMAT_YCrCb_422_SP_10B : src0_format = 0x8; xdiv = 1; ydiv = 1; src0_cbcr_swp = 1; yuv10 = 1; break;
284
285 case RGA2_FORMAT_YCbCr_400 : src0_format = 0x8; src_fmt_yuv400_en = 1; xdiv = 1; ydiv = 1; break;
286 };
287
288 reg = ((reg & (~m_RGA2_SRC_INFO_SW_SRC_FMT)) | (s_RGA2_SRC_INFO_SW_SRC_FMT(src0_format)));
289 reg = ((reg & (~m_RGA2_SRC_INFO_SW_SW_SRC_RB_SWAP)) | (s_RGA2_SRC_INFO_SW_SW_SRC_RB_SWAP(src0_rb_swp)));
290 reg = ((reg & (~m_RGA2_SRC_INFO_SW_SW_SRC_ALPHA_SWAP)) | (s_RGA2_SRC_INFO_SW_SW_SRC_ALPHA_SWAP(src0_alpha_swp)));
291 reg = ((reg & (~m_RGA2_SRC_INFO_SW_SW_SRC_UV_SWAP)) | (s_RGA2_SRC_INFO_SW_SW_SRC_UV_SWAP(src0_cbcr_swp)));
292 reg = ((reg & (~m_RGA2_SRC_INFO_SW_SW_SRC_CSC_MODE)) | (s_RGA2_SRC_INFO_SW_SW_SRC_CSC_MODE(msg->yuv2rgb_mode)));
293
294 reg = ((reg & (~m_RGA2_SRC_INFO_SW_SW_SRC_ROT_MODE)) | (s_RGA2_SRC_INFO_SW_SW_SRC_ROT_MODE(msg->rotate_mode & 0x3)));
295 reg = ((reg & (~m_RGA2_SRC_INFO_SW_SW_SRC_MIR_MODE)) | (s_RGA2_SRC_INFO_SW_SW_SRC_MIR_MODE((msg->rotate_mode >> 4) & 0x3)));
296 reg = ((reg & (~m_RGA2_SRC_INFO_SW_SW_SRC_HSCL_MODE)) | (s_RGA2_SRC_INFO_SW_SW_SRC_HSCL_MODE((scale_w_flag))));
297 reg = ((reg & (~m_RGA2_SRC_INFO_SW_SW_SRC_VSCL_MODE)) | (s_RGA2_SRC_INFO_SW_SW_SRC_VSCL_MODE((scale_h_flag))));
298 reg = ((reg & (~m_RGA2_SRC_INFO_SW_SW_SRC_SCL_FILTER)) | (s_RGA2_SRC_INFO_SW_SW_SRC_SCL_FILTER((msg->scale_bicu_mode))));
299 reg = ((reg & (~m_RGA2_SRC_INFO_SW_SW_SRC_TRANS_MODE)) | (s_RGA2_SRC_INFO_SW_SW_SRC_TRANS_MODE(msg->src_trans_mode)));
300 reg = ((reg & (~m_RGA2_SRC_INFO_SW_SW_SRC_TRANS_E)) | (s_RGA2_SRC_INFO_SW_SW_SRC_TRANS_E(msg->src_trans_mode >> 1)));
301 reg = ((reg & (~m_RGA2_SRC_INFO_SW_SW_SRC_DITHER_UP_E)) | (s_RGA2_SRC_INFO_SW_SW_SRC_DITHER_UP_E((msg->alpha_rop_flag >> 4) & 0x1)));
302 reg = ((reg & (~m_RGA2_SRC_INFO_SW_SW_VSP_MODE_SEL)) | (s_RGA2_SRC_INFO_SW_SW_VSP_MODE_SEL((msg->scale_bicu_mode>>4))));
303 reg = ((reg & (~m_RGA2_SRC_INFO_SW_SW_YUV10_E)) | (s_RGA2_SRC_INFO_SW_SW_YUV10_E((yuv10))));
304 #if 1
305 reg = ((reg & (~m_RGA2_SRC_INFO_SW_SW_YUV10_ROUND_E)) | (s_RGA2_SRC_INFO_SW_SW_YUV10_ROUND_E((yuv10))));
306 #else
307 reg = ((reg & (~m_RGA2_SRC_INFO_SW_SW_YUV10_ROUND_E)) | (s_RGA2_SRC_INFO_SW_SW_YUV10_ROUND_E(((msg->yuv2rgb_mode >> 6)&1))));
308 #endif
309 RGA2_reg_get_param(base, msg);
310
311 stride = (((msg->src.vir_w * pixel_width) + 3) & ~3) >> 2;
312 uv_stride = ((msg->src.vir_w / xdiv + 3) & ~3);
313
314 /* 10bit code */
315 #if 0
316 switch (msg->src.format)
317 {
318 case RGA2_FORMAT_YCbCr_422_SP_10B:
319 case RGA2_FORMAT_YCbCr_420_SP_10B:
320 case RGA2_FORMAT_YCrCb_422_SP_10B:
321 case RGA2_FORMAT_YCrCb_420_SP_10B:
322 stride = (((msg->src.vir_w * 10 + 31) & (~31)) >> 3) >> 2;
323 uv_stride = stride;
324 break;
325 }
326 #endif
327
328 if (src_fmt_yuv400_en == 1) {
329 /*
330 * When Y400 as the input format, because the current RGA does not support closing
331 * the access of the UV channel, the address of the UV channel access is equal to
332 * the address of the Y channel access to ensure that the UV channel can access,
333 * preventing the RGA hardware from reporting errors.
334 */
335 *bRGA_SRC_BASE0 = (RK_U32)(msg->src.yrgb_addr + msg->src.y_offset * (stride<<2) + msg->src.x_offset * pixel_width);
336 *bRGA_SRC_BASE1 = *bRGA_SRC_BASE0;
337 *bRGA_SRC_BASE2 = *bRGA_SRC_BASE0;
338 } else {
339 *bRGA_SRC_BASE0 = (RK_U32)(msg->src.yrgb_addr + msg->src.y_offset * (stride<<2) + msg->src.x_offset * pixel_width);
340 *bRGA_SRC_BASE1 = (RK_U32)(msg->src.uv_addr + (msg->src.y_offset / ydiv) * uv_stride + (msg->src.x_offset / xdiv));
341 *bRGA_SRC_BASE2 = (RK_U32)(msg->src.v_addr + (msg->src.y_offset / ydiv) * uv_stride + (msg->src.x_offset / xdiv));
342 }
343
344 //mask_stride = ((msg->src0_act.width + 31) & ~31) >> 5;
345 mask_stride = msg->rop_mask_stride;
346
347 *bRGA_SRC_VIR_INFO = stride | (mask_stride << 16);
348
349 *bRGA_SRC_ACT_INFO = (msg->src.act_w - 1) | ((msg->src.act_h - 1) << 16);
350
351 *bRGA_MASK_ADDR = (RK_U32)msg->rop_mask_addr;
352
353 *bRGA_SRC_INFO = reg;
354
355 *bRGA_SRC_TR_COLOR0 = msg->color_key_min;
356 *bRGA_SRC_TR_COLOR1 = msg->color_key_max;
357 }
358
RGA2_set_reg_dst_info(u8 * base,struct rga2_req * msg)359 static void RGA2_set_reg_dst_info(u8 *base, struct rga2_req *msg)
360 {
361 RK_U32 *bRGA_DST_INFO;
362 RK_U32 *bRGA_DST_BASE0, *bRGA_DST_BASE1, *bRGA_DST_BASE2, *bRGA_SRC_BASE3;
363 RK_U32 *bRGA_DST_VIR_INFO;
364 RK_U32 *bRGA_DST_ACT_INFO;
365
366 RK_U32 *RGA_DST_Y4MAP_LUT0;//Y4 LUT0
367 RK_U32 *RGA_DST_Y4MAP_LUT1;//Y4 LUT1
368 RK_U32 *RGA_DST_NN_QUANTIZE_SCALE;
369 RK_U32 *RGA_DST_NN_QUANTIZE_OFFSET;
370
371 RK_U32 line_width_real;
372
373 RK_U8 ydither_en = 0;
374
375 RK_U8 src1_format = 0;
376 RK_U8 src1_rb_swp = 0;
377 RK_U8 src1_rgb_pack = 0;
378 RK_U8 src1_alpha_swp = 0;
379 RK_U8 dst_format = 0;
380 RK_U8 dst_rb_swp = 0;
381 RK_U8 dst_rgb_pack = 0;
382 RK_U8 dst_cbcr_swp = 0;
383 RK_U8 dst_alpha_swp = 0;
384
385 RK_U8 dst_fmt_yuv400_en = 0;
386 RK_U8 dst_fmt_y4_en = 0;
387 RK_U8 dst_nn_quantize_en = 0;
388
389 RK_U32 reg = 0;
390 RK_U8 spw, dpw;
391 RK_U32 s_stride, d_stride;
392 RK_U32 x_mirr, y_mirr, rot_90_flag;
393 RK_U32 yrgb_addr, u_addr, v_addr, s_yrgb_addr;
394 RK_U32 d_uv_stride, x_div, y_div;
395 RK_U32 y_lt_addr, y_ld_addr, y_rt_addr, y_rd_addr;
396 RK_U32 u_lt_addr, u_ld_addr, u_rt_addr, u_rd_addr;
397 RK_U32 v_lt_addr, v_ld_addr, v_rt_addr, v_rd_addr;
398
399 dpw = 1;
400 x_div = y_div = 1;
401
402 dst_nn_quantize_en = (msg->alpha_rop_flag >> 8)&0x1;
403
404 bRGA_DST_INFO = (RK_U32 *)(base + RGA2_DST_INFO_OFFSET);
405 bRGA_DST_BASE0 = (RK_U32 *)(base + RGA2_DST_BASE0_OFFSET);
406 bRGA_DST_BASE1 = (RK_U32 *)(base + RGA2_DST_BASE1_OFFSET);
407 bRGA_DST_BASE2 = (RK_U32 *)(base + RGA2_DST_BASE2_OFFSET);
408
409 bRGA_SRC_BASE3 = (RK_U32 *)(base + RGA2_SRC_BASE3_OFFSET);
410
411 bRGA_DST_VIR_INFO = (RK_U32 *)(base + RGA2_DST_VIR_INFO_OFFSET);
412 bRGA_DST_ACT_INFO = (RK_U32 *)(base + RGA2_DST_ACT_INFO_OFFSET);
413
414 RGA_DST_Y4MAP_LUT0 = (RK_U32 *)(base + RGA2_DST_Y4MAP_LUT0_OFFSET);
415 RGA_DST_Y4MAP_LUT1 = (RK_U32 *)(base + RGA2_DST_Y4MAP_LUT1_OFFSET);
416 RGA_DST_NN_QUANTIZE_SCALE = (RK_U32 *)(base + RGA2_DST_QUANTIZE_SCALE_OFFSET);
417 RGA_DST_NN_QUANTIZE_OFFSET = (RK_U32 *)(base + RGA2_DST_QUANTIZE_OFFSET_OFFSET);
418
419 switch (msg->src1.format)
420 {
421 case RGA2_FORMAT_RGBA_8888 : src1_format = 0x0; spw = 4; break;
422 case RGA2_FORMAT_BGRA_8888 : src1_format = 0x0; src1_rb_swp = 0x1; spw = 4; break;
423 case RGA2_FORMAT_RGBX_8888 : src1_format = 0x1; spw = 4; break;
424 case RGA2_FORMAT_BGRX_8888 : src1_format = 0x1; src1_rb_swp = 0x1; spw = 4; break;
425 case RGA2_FORMAT_RGB_888 : src1_format = 0x2; src1_rgb_pack = 1; spw = 3; break;
426 case RGA2_FORMAT_BGR_888 : src1_format = 0x2; src1_rgb_pack = 1; src1_rb_swp = 1; spw = 3; break;
427 case RGA2_FORMAT_RGB_565 : src1_format = 0x4; spw = 2; break;
428 case RGA2_FORMAT_RGBA_5551 : src1_format = 0x5; spw = 2; src1_rb_swp = 0x1; break;
429 case RGA2_FORMAT_RGBA_4444 : src1_format = 0x6; spw = 2; src1_rb_swp = 0x1; break;
430 case RGA2_FORMAT_BGR_565 : src1_format = 0x4; spw = 2; src1_rb_swp = 0x1; break;
431 case RGA2_FORMAT_BGRA_5551 : src1_format = 0x5; spw = 2; break;
432 case RGA2_FORMAT_BGRA_4444 : src1_format = 0x6; spw = 2; break;
433
434 /* ARGB */
435 case RGA2_FORMAT_ARGB_8888 : src1_format = 0x0; spw = 4; src1_alpha_swp = 1; break;
436 case RGA2_FORMAT_ABGR_8888 : src1_format = 0x0; spw = 4; src1_alpha_swp = 1; src1_rb_swp = 0x1; break;
437 case RGA2_FORMAT_XRGB_8888 : src1_format = 0x1; spw = 4; src1_alpha_swp = 1; break;
438 case RGA2_FORMAT_XBGR_8888 : src1_format = 0x1; spw = 4; src1_alpha_swp = 1; src1_rb_swp = 0x1; break;
439 case RGA2_FORMAT_ARGB_5551 : src1_format = 0x5; spw = 2; src1_alpha_swp = 1; break;
440 case RGA2_FORMAT_ABGR_5551 : src1_format = 0x5; spw = 2; src1_alpha_swp = 1; src1_rb_swp = 0x1; break;
441 case RGA2_FORMAT_ARGB_4444 : src1_format = 0x6; spw = 2; src1_alpha_swp = 1; break;
442 case RGA2_FORMAT_ABGR_4444 : src1_format = 0x6; spw = 2; src1_alpha_swp = 1; src1_rb_swp = 0x1; break;
443 default : spw = 4; break;
444 };
445
446 reg = ((reg & (~m_RGA2_DST_INFO_SW_SRC1_FMT)) | (s_RGA2_DST_INFO_SW_SRC1_FMT(src1_format)));
447 reg = ((reg & (~m_RGA2_DST_INFO_SW_SRC1_RB_SWP)) | (s_RGA2_DST_INFO_SW_SRC1_RB_SWP(src1_rb_swp)));
448 reg = ((reg & (~m_RGA2_DST_INFO_SW_SRC1_ALPHA_SWP)) | (s_RGA2_DST_INFO_SW_SRC1_ALPHA_SWP(src1_alpha_swp)));
449
450
451 switch (msg->dst.format)
452 {
453 case RGA2_FORMAT_RGBA_8888 : dst_format = 0x0; dpw = 4; break;
454 case RGA2_FORMAT_BGRA_8888 : dst_format = 0x0; dst_rb_swp = 0x1; dpw = 4; break;
455 case RGA2_FORMAT_RGBX_8888 : dst_format = 0x1; dpw = 4; break;
456 case RGA2_FORMAT_BGRX_8888 : dst_format = 0x1; dst_rb_swp = 0x1; dpw = 4; break;
457 case RGA2_FORMAT_RGB_888 : dst_format = 0x2; dst_rgb_pack = 1; dpw = 3; break;
458 case RGA2_FORMAT_BGR_888 : dst_format = 0x2; dst_rgb_pack = 1; dst_rb_swp = 1; dpw = 3; break;
459 case RGA2_FORMAT_RGB_565 : dst_format = 0x4; dpw = 2; break;
460 case RGA2_FORMAT_RGBA_5551 : dst_format = 0x5; dpw = 2; dst_rb_swp = 0x1; break;
461 case RGA2_FORMAT_RGBA_4444 : dst_format = 0x6; dpw = 2; dst_rb_swp = 0x1; break;
462 case RGA2_FORMAT_BGR_565 : dst_format = 0x4; dpw = 2; dst_rb_swp = 0x1; break;
463 case RGA2_FORMAT_BGRA_5551 : dst_format = 0x5; dpw = 2; break;
464 case RGA2_FORMAT_BGRA_4444 : dst_format = 0x6; dpw = 2; break;
465
466 /* ARGB */
467 case RGA2_FORMAT_ARGB_8888 : dst_format = 0x0; dpw = 4; dst_alpha_swp = 1; break;
468 case RGA2_FORMAT_ABGR_8888 : dst_format = 0x0; dpw = 4; dst_alpha_swp = 1; dst_rb_swp = 0x1; break;
469 case RGA2_FORMAT_XRGB_8888 : dst_format = 0x1; dpw = 4; dst_alpha_swp = 1; break;
470 case RGA2_FORMAT_XBGR_8888 : dst_format = 0x1; dpw = 4; dst_alpha_swp = 1; dst_rb_swp = 0x1; break;
471 case RGA2_FORMAT_ARGB_5551 : dst_format = 0x5; dpw = 2; dst_alpha_swp = 1; break;
472 case RGA2_FORMAT_ABGR_5551 : dst_format = 0x5; dpw = 2; dst_alpha_swp = 1; dst_rb_swp = 0x1; break;
473 case RGA2_FORMAT_ARGB_4444 : dst_format = 0x6; dpw = 2; dst_alpha_swp = 1; break;
474 case RGA2_FORMAT_ABGR_4444 : dst_format = 0x6; dpw = 2; dst_alpha_swp = 1; dst_rb_swp = 0x1; break;
475
476 case RGA2_FORMAT_YCbCr_422_SP : dst_format = 0x8; x_div = 1; y_div = 1; break;
477 case RGA2_FORMAT_YCbCr_422_P : dst_format = 0x9; x_div = 2; y_div = 1; break;
478 case RGA2_FORMAT_YCbCr_420_SP : dst_format = 0xa; x_div = 1; y_div = 2; break;
479 case RGA2_FORMAT_YCbCr_420_P : dst_format = 0xb; dst_cbcr_swp = 1; x_div = 2; y_div = 2; break;
480 case RGA2_FORMAT_YCrCb_422_SP : dst_format = 0x8; dst_cbcr_swp = 1; x_div = 1; y_div = 1; break;
481 case RGA2_FORMAT_YCrCb_422_P : dst_format = 0x9; dst_cbcr_swp = 1; x_div = 2; y_div = 1; break;
482 case RGA2_FORMAT_YCrCb_420_SP : dst_format = 0xa; dst_cbcr_swp = 1; x_div = 1; y_div = 2; break;
483 case RGA2_FORMAT_YCrCb_420_P : dst_format = 0xb; x_div = 2; y_div = 2; break;
484
485 case RGA2_FORMAT_YCbCr_400 : dst_format = 0x8; dst_fmt_yuv400_en = 1; x_div = 1; y_div = 1; break;
486 case RGA2_FORMAT_Y4 : dst_format = 0x8; dst_fmt_y4_en = 1; dst_fmt_yuv400_en = 1; x_div = 1; y_div = 1; break;
487
488 case RGA2_FORMAT_YUYV_422 : dst_format = 0xe; dpw = 2; dst_cbcr_swp = 1; break;
489 case RGA2_FORMAT_YVYU_422 : dst_format = 0xe; dpw = 2; break;
490 case RGA2_FORMAT_YUYV_420 : dst_format = 0xf; dpw = 2; dst_cbcr_swp = 1; break;
491 case RGA2_FORMAT_YVYU_420 : dst_format = 0xf; dpw = 2; break;
492 case RGA2_FORMAT_UYVY_422 : dst_format = 0xc; dpw = 2; dst_cbcr_swp = 1; break;
493 case RGA2_FORMAT_VYUY_422 : dst_format = 0xc; dpw = 2; break;
494 case RGA2_FORMAT_UYVY_420 : dst_format = 0xd; dpw = 2; dst_cbcr_swp = 1; break;
495 case RGA2_FORMAT_VYUY_420 : dst_format = 0xd; dpw = 2; break;
496 };
497
498 reg = ((reg & (~m_RGA2_DST_INFO_SW_DST_FMT)) | (s_RGA2_DST_INFO_SW_DST_FMT(dst_format)));
499 reg = ((reg & (~m_RGA2_DST_INFO_SW_DST_RB_SWAP)) | (s_RGA2_DST_INFO_SW_DST_RB_SWAP(dst_rb_swp)));
500 reg = ((reg & (~m_RGA2_DST_INFO_SW_ALPHA_SWAP)) | (s_RGA2_DST_INFO_SW_ALPHA_SWAP(dst_alpha_swp)));
501 reg = ((reg & (~m_RGA2_DST_INFO_SW_DST_UV_SWAP)) | (s_RGA2_DST_INFO_SW_DST_UV_SWAP(dst_cbcr_swp)));
502
503 reg = ((reg & (~m_RGA2_DST_INFO_SW_DST_FMT_YUV400_EN)) | (s_RGA2_DST_INFO_SW_DST_FMT_YUV400_EN(dst_fmt_yuv400_en)));
504 reg = ((reg & (~m_RGA2_DST_INFO_SW_DST_FMT_Y4_EN)) | (s_RGA2_DST_INFO_SW_DST_FMT_Y4_EN(dst_fmt_y4_en)));
505 reg = ((reg & (~m_RGA2_DST_INFO_SW_DST_NN_QUANTIZE_EN)) | (s_RGA2_DST_INFO_SW_DST_NN_QUANTIZE_EN(dst_nn_quantize_en)));
506 reg = ((reg & (~m_RGA2_DST_INFO_SW_DITHER_UP_E)) | (s_RGA2_DST_INFO_SW_DITHER_UP_E(msg->alpha_rop_flag >> 5)));
507 reg = ((reg & (~m_RGA2_DST_INFO_SW_DITHER_DOWN_E)) | (s_RGA2_DST_INFO_SW_DITHER_DOWN_E(msg->alpha_rop_flag >> 6)));
508 reg = ((reg & (~m_RGA2_DST_INFO_SW_DITHER_MODE)) | (s_RGA2_DST_INFO_SW_DITHER_MODE(msg->dither_mode)));
509 reg = ((reg & (~m_RGA2_DST_INFO_SW_DST_CSC_MODE)) | (s_RGA2_DST_INFO_SW_DST_CSC_MODE(msg->yuv2rgb_mode >> 2)));
510 reg = ((reg & (~m_RGA2_DST_INFO_SW_CSC_CLIP_MODE)) | (s_RGA2_DST_INFO_SW_CSC_CLIP_MODE(msg->yuv2rgb_mode >> 4)));
511 /* full csc enable */
512 reg = ((reg & (~m_RGA2_DST_INFO_SW_DST_CSC_MODE_2)) | (s_RGA2_DST_INFO_SW_DST_CSC_MODE_2(msg->full_csc.flag)));
513 /* Some older chips do not support src1 csc mode, they do not have these two registers. */
514 reg = ((reg & (~m_RGA2_DST_INFO_SW_SRC1_CSC_MODE)) | (s_RGA2_DST_INFO_SW_SRC1_CSC_MODE(msg->yuv2rgb_mode >> 5)));
515 reg = ((reg & (~m_RGA2_DST_INFO_SW_SRC1_CSC_CLIP_MODE)) | (s_RGA2_DST_INFO_SW_SRC1_CSC_CLIP_MODE(msg->yuv2rgb_mode >> 7)));
516
517 ydither_en = (msg->dst.format == RGA2_FORMAT_Y4) && ((msg->alpha_rop_flag >> 6)&0x1);
518
519 *bRGA_DST_INFO = reg;
520
521 s_stride = ((msg->src1.vir_w * spw + 3) & ~3) >> 2;
522 d_stride = ((msg->dst.vir_w * dpw + 3) & ~3) >> 2;
523
524 if (dst_fmt_y4_en) {
525 /* Y4 output will HALF */
526 d_stride = ((d_stride+1)&~1) >> 1;
527 }
528
529 d_uv_stride = (d_stride << 2) / x_div;
530
531 *bRGA_DST_VIR_INFO = d_stride | (s_stride << 16);
532 if ((msg->dst.vir_w % 2 != 0) &&
533 (msg->dst.act_w == msg->src.act_w) && (msg->dst.act_h == msg->src.act_h) &&
534 (msg->dst.format == RGA2_FORMAT_BGR_888 || msg->dst.format == RGA2_FORMAT_RGB_888))
535 *bRGA_DST_ACT_INFO = (msg->dst.act_w) | ((msg->dst.act_h - 1) << 16);
536 else
537 *bRGA_DST_ACT_INFO = (msg->dst.act_w - 1) | ((msg->dst.act_h - 1) << 16);
538 s_stride <<= 2;
539 d_stride <<= 2;
540
541 if(((msg->rotate_mode & 0xf) == 0) || ((msg->rotate_mode & 0xf) == 1))
542 {
543 x_mirr = 0;
544 y_mirr = 0;
545 }
546 else
547 {
548 x_mirr = 1;
549 y_mirr = 1;
550 }
551
552 rot_90_flag = msg->rotate_mode & 1;
553 x_mirr = (x_mirr + ((msg->rotate_mode >> 4) & 1)) & 1;
554 y_mirr = (y_mirr + ((msg->rotate_mode >> 5) & 1)) & 1;
555
556 if (ydither_en) {
557 if (x_mirr && y_mirr) {
558 printk(KERN_ERR "rga: [ERROR] YDITHER MODE DO NOT SUPPORT ROTATION !!x_mirr=%d,y_mirr=%d \n", x_mirr, y_mirr);
559 }
560 if (msg->dst.act_w != msg->src.act_w) {
561 printk(KERN_ERR "rga: [ERROR] YDITHER MODE DO NOT SUPPORT SCL !!src0.act_w=%d,dst.act_w=%d \n", msg->src.act_w, msg->dst.act_w);
562 }
563 if (msg->dst.act_h != msg->src.act_h) {
564 printk(KERN_ERR "rga: [ERROR] YDITHER MODE DO NOT SUPPORT SCL !!src0.act_h=%d,dst.act_h=%d \n", msg->src.act_h, msg->dst.act_h);
565 }
566 }
567
568 if (dst_fmt_y4_en) {
569 *RGA_DST_Y4MAP_LUT0 = (msg->gr_color.gr_x_r & 0xffff) | (msg->gr_color.gr_x_g << 16);
570 *RGA_DST_Y4MAP_LUT1 = (msg->gr_color.gr_y_r & 0xffff) | (msg->gr_color.gr_y_g << 16);
571 }
572
573 if (dst_nn_quantize_en) {
574 *RGA_DST_NN_QUANTIZE_SCALE = (msg->gr_color.gr_x_r & 0xffff) | (msg->gr_color.gr_x_g << 10) | (msg->gr_color.gr_x_b << 20);
575 *RGA_DST_NN_QUANTIZE_OFFSET = (msg->gr_color.gr_y_r & 0xffff) | (msg->gr_color.gr_y_g << 10) | (msg->gr_color.gr_y_b << 20);
576 }
577
578 s_yrgb_addr = (RK_U32)msg->src1.yrgb_addr + (msg->src1.y_offset * s_stride) + (msg->src1.x_offset * spw);
579
580 *bRGA_SRC_BASE3 = s_yrgb_addr;
581
582 if (dst_fmt_y4_en) {
583 yrgb_addr = (RK_U32)msg->dst.yrgb_addr + (msg->dst.y_offset * d_stride) + ((msg->dst.x_offset * dpw)>>1);
584 } else {
585 yrgb_addr = (RK_U32)msg->dst.yrgb_addr + (msg->dst.y_offset * d_stride) + (msg->dst.x_offset * dpw);
586 }
587 u_addr = (RK_U32)msg->dst.uv_addr + (msg->dst.y_offset / y_div) * d_uv_stride + msg->dst.x_offset / x_div;
588 v_addr = (RK_U32)msg->dst.v_addr + (msg->dst.y_offset / y_div) * d_uv_stride + msg->dst.x_offset / x_div;
589
590 y_lt_addr = yrgb_addr;
591 u_lt_addr = u_addr;
592 v_lt_addr = v_addr;
593
594 /* Warning */
595 line_width_real = dst_fmt_y4_en ? ((msg->dst.act_w) >>1) : msg->dst.act_w;
596
597 if (msg->dst.format < 0x18 ||
598 (msg->dst.format >= RGA2_FORMAT_ARGB_8888 &&
599 msg->dst.format <= RGA2_FORMAT_ABGR_4444)) {
600 /* 270 degree & Mirror V*/
601 y_ld_addr = yrgb_addr + (msg->dst.act_h - 1) * (d_stride);
602 /* 90 degree & Mirror H */
603 y_rt_addr = yrgb_addr + (line_width_real - 1) * dpw;
604 /* 180 degree */
605 y_rd_addr = y_ld_addr + (line_width_real - 1) * dpw;
606 } else {
607 if (msg->dst.format == RGA2_FORMAT_YUYV_422 ||
608 msg->dst.format == RGA2_FORMAT_YVYU_422 ||
609 msg->dst.format == RGA2_FORMAT_UYVY_422 ||
610 msg->dst.format == RGA2_FORMAT_VYUY_422) {
611 y_ld_addr = yrgb_addr + (msg->dst.act_h - 1) * (d_stride);
612 y_rt_addr = yrgb_addr + (msg->dst.act_w * 2 - 1);
613 y_rd_addr = y_ld_addr + (msg->dst.act_w * 2 - 1);
614 } else {
615 y_ld_addr = (RK_U32)msg->dst.yrgb_addr +
616 ((msg->dst.y_offset + (msg->dst.act_h -1)) * d_stride) +
617 msg->dst.x_offset;
618 y_rt_addr = yrgb_addr + (msg->dst.act_w * 2 - 1);
619 y_rd_addr = y_ld_addr + (msg->dst.act_w - 1);
620 }
621 }
622
623 u_ld_addr = u_addr + ((msg->dst.act_h / y_div) - 1) * (d_uv_stride);
624 v_ld_addr = v_addr + ((msg->dst.act_h / y_div) - 1) * (d_uv_stride);
625
626 u_rt_addr = u_addr + (msg->dst.act_w / x_div) - 1;
627 v_rt_addr = v_addr + (msg->dst.act_w / x_div) - 1;
628
629 u_rd_addr = u_ld_addr + (msg->dst.act_w / x_div) - 1;
630 v_rd_addr = v_ld_addr + (msg->dst.act_w / x_div) - 1;
631
632 if(rot_90_flag == 0)
633 {
634 if(y_mirr == 1)
635 {
636 if(x_mirr == 1)
637 {
638 yrgb_addr = y_rd_addr;
639 u_addr = u_rd_addr;
640 v_addr = v_rd_addr;
641 }
642 else
643 {
644 yrgb_addr = y_ld_addr;
645 u_addr = u_ld_addr;
646 v_addr = v_ld_addr;
647 }
648 }
649 else
650 {
651 if(x_mirr == 1)
652 {
653 yrgb_addr = y_rt_addr;
654 u_addr = u_rt_addr;
655 v_addr = v_rt_addr;
656 }
657 else
658 {
659 yrgb_addr = y_lt_addr;
660 u_addr = u_lt_addr;
661 v_addr = v_lt_addr;
662 }
663 }
664 }
665 else
666 {
667 if(y_mirr == 1)
668 {
669 if(x_mirr == 1)
670 {
671 yrgb_addr = y_ld_addr;
672 u_addr = u_ld_addr;
673 v_addr = v_ld_addr;
674 }
675 else
676 {
677 yrgb_addr = y_rd_addr;
678 u_addr = u_rd_addr;
679 v_addr = v_rd_addr;
680 }
681 }
682 else
683 {
684 if(x_mirr == 1)
685 {
686 yrgb_addr = y_lt_addr;
687 u_addr = u_lt_addr;
688 v_addr = v_lt_addr;
689 }
690 else
691 {
692 yrgb_addr = y_rt_addr;
693 u_addr = u_rt_addr;
694 v_addr = v_rt_addr;
695 }
696 }
697 }
698
699 *bRGA_DST_BASE0 = (RK_U32)yrgb_addr;
700
701 if((msg->dst.format == RGA2_FORMAT_YCbCr_420_P) || (msg->dst.format == RGA2_FORMAT_YCrCb_420_P))
702 {
703 if(dst_cbcr_swp == 0) {
704 *bRGA_DST_BASE1 = (RK_U32)v_addr;
705 *bRGA_DST_BASE2 = (RK_U32)u_addr;
706 }
707 else {
708 *bRGA_DST_BASE1 = (RK_U32)u_addr;
709 *bRGA_DST_BASE2 = (RK_U32)v_addr;
710 }
711 }
712 else {
713 *bRGA_DST_BASE1 = (RK_U32)u_addr;
714 *bRGA_DST_BASE2 = (RK_U32)v_addr;
715 }
716
717 //if (msg->dst.format >= 0x18) {
718 // *bRGA_DST_BASE1 = msg->dst.x_offset;
719 //}
720 }
721
RGA2_set_reg_alpha_info(u8 * base,struct rga2_req * msg)722 static void RGA2_set_reg_alpha_info(u8 *base, struct rga2_req *msg)
723 {
724 RK_U32 *bRGA_ALPHA_CTRL0;
725 RK_U32 *bRGA_ALPHA_CTRL1;
726 RK_U32 *bRGA_FADING_CTRL;
727 RK_U32 reg0 = 0;
728 RK_U32 reg1 = 0;
729
730 bRGA_ALPHA_CTRL0 = (RK_U32 *)(base + RGA2_ALPHA_CTRL0_OFFSET);
731 bRGA_ALPHA_CTRL1 = (RK_U32 *)(base + RGA2_ALPHA_CTRL1_OFFSET);
732 bRGA_FADING_CTRL = (RK_U32 *)(base + RGA2_FADING_CTRL_OFFSET);
733
734 reg0 = ((reg0 & (~m_RGA2_ALPHA_CTRL0_SW_ALPHA_ROP_0)) | (s_RGA2_ALPHA_CTRL0_SW_ALPHA_ROP_0(msg->alpha_rop_flag)));
735 reg0 = ((reg0 & (~m_RGA2_ALPHA_CTRL0_SW_ALPHA_ROP_SEL)) | (s_RGA2_ALPHA_CTRL0_SW_ALPHA_ROP_SEL(msg->alpha_rop_flag >> 1)));
736 reg0 = ((reg0 & (~m_RGA2_ALPHA_CTRL0_SW_ROP_MODE)) | (s_RGA2_ALPHA_CTRL0_SW_ROP_MODE(msg->rop_mode)));
737 reg0 = ((reg0 & (~m_RGA2_ALPHA_CTRL0_SW_SRC_GLOBAL_ALPHA)) | (s_RGA2_ALPHA_CTRL0_SW_SRC_GLOBAL_ALPHA(msg->src_a_global_val)));
738 reg0 = ((reg0 & (~m_RGA2_ALPHA_CTRL0_SW_DST_GLOBAL_ALPHA)) | (s_RGA2_ALPHA_CTRL0_SW_DST_GLOBAL_ALPHA(msg->dst_a_global_val)));
739
740 reg1 = ((reg1 & (~m_RGA2_ALPHA_CTRL1_SW_DST_COLOR_M0)) | (s_RGA2_ALPHA_CTRL1_SW_DST_COLOR_M0(msg->alpha_mode_0 >> 15)));
741 reg1 = ((reg1 & (~m_RGA2_ALPHA_CTRL1_SW_SRC_COLOR_M0)) | (s_RGA2_ALPHA_CTRL1_SW_SRC_COLOR_M0(msg->alpha_mode_0 >> 7)));
742 reg1 = ((reg1 & (~m_RGA2_ALPHA_CTRL1_SW_DST_FACTOR_M0)) | (s_RGA2_ALPHA_CTRL1_SW_DST_FACTOR_M0(msg->alpha_mode_0 >> 12)));
743 reg1 = ((reg1 & (~m_RGA2_ALPHA_CTRL1_SW_SRC_FACTOR_M0)) | (s_RGA2_ALPHA_CTRL1_SW_SRC_FACTOR_M0(msg->alpha_mode_0 >> 4)));
744 reg1 = ((reg1 & (~m_RGA2_ALPHA_CTRL1_SW_DST_ALPHA_CAL_M0)) | (s_RGA2_ALPHA_CTRL1_SW_DST_ALPHA_CAL_M0(msg->alpha_mode_0 >> 11)));
745 reg1 = ((reg1 & (~m_RGA2_ALPHA_CTRL1_SW_SRC_ALPHA_CAL_M0)) | (s_RGA2_ALPHA_CTRL1_SW_SRC_ALPHA_CAL_M0(msg->alpha_mode_0 >> 3)));
746 reg1 = ((reg1 & (~m_RGA2_ALPHA_CTRL1_SW_DST_BLEND_M0)) | (s_RGA2_ALPHA_CTRL1_SW_DST_BLEND_M0(msg->alpha_mode_0 >> 9)));
747 reg1 = ((reg1 & (~m_RGA2_ALPHA_CTRL1_SW_SRC_BLEND_M0)) | (s_RGA2_ALPHA_CTRL1_SW_SRC_BLEND_M0(msg->alpha_mode_0 >> 1)));
748 reg1 = ((reg1 & (~m_RGA2_ALPHA_CTRL1_SW_DST_ALPHA_M0)) | (s_RGA2_ALPHA_CTRL1_SW_DST_ALPHA_M0(msg->alpha_mode_0 >> 8)));
749 reg1 = ((reg1 & (~m_RGA2_ALPHA_CTRL1_SW_SRC_ALPHA_M0)) | (s_RGA2_ALPHA_CTRL1_SW_SRC_ALPHA_M0(msg->alpha_mode_0 >> 0)));
750
751 reg1 = ((reg1 & (~m_RGA2_ALPHA_CTRL1_SW_DST_FACTOR_M1)) | (s_RGA2_ALPHA_CTRL1_SW_DST_FACTOR_M1(msg->alpha_mode_1 >> 12)));
752 reg1 = ((reg1 & (~m_RGA2_ALPHA_CTRL1_SW_SRC_FACTOR_M1)) | (s_RGA2_ALPHA_CTRL1_SW_SRC_FACTOR_M1(msg->alpha_mode_1 >> 4)));
753 reg1 = ((reg1 & (~m_RGA2_ALPHA_CTRL1_SW_DST_ALPHA_CAL_M1)) | (s_RGA2_ALPHA_CTRL1_SW_DST_ALPHA_CAL_M1(msg->alpha_mode_1 >> 11)));
754 reg1 = ((reg1 & (~m_RGA2_ALPHA_CTRL1_SW_SRC_ALPHA_CAL_M1)) | (s_RGA2_ALPHA_CTRL1_SW_SRC_ALPHA_CAL_M1(msg->alpha_mode_1 >> 3)));
755 reg1 = ((reg1 & (~m_RGA2_ALPHA_CTRL1_SW_DST_BLEND_M1)) | (s_RGA2_ALPHA_CTRL1_SW_DST_BLEND_M1(msg->alpha_mode_1 >> 9)));
756 reg1 = ((reg1 & (~m_RGA2_ALPHA_CTRL1_SW_SRC_BLEND_M1)) | (s_RGA2_ALPHA_CTRL1_SW_SRC_BLEND_M1(msg->alpha_mode_1 >> 1)));
757 reg1 = ((reg1 & (~m_RGA2_ALPHA_CTRL1_SW_DST_ALPHA_M1)) | (s_RGA2_ALPHA_CTRL1_SW_DST_ALPHA_M1(msg->alpha_mode_1 >> 8)));
758 reg1 = ((reg1 & (~m_RGA2_ALPHA_CTRL1_SW_SRC_ALPHA_M1)) | (s_RGA2_ALPHA_CTRL1_SW_SRC_ALPHA_M1(msg->alpha_mode_1 >> 0)));
759
760 *bRGA_ALPHA_CTRL0 = reg0;
761 *bRGA_ALPHA_CTRL1 = reg1;
762
763 if((msg->alpha_rop_flag>>2)&1)
764 {
765 *bRGA_FADING_CTRL = (1<<24) | (msg->fading_b_value<<16) | (msg->fading_g_value<<8) | (msg->fading_r_value);
766 }
767 }
768
RGA2_set_reg_rop_info(u8 * base,struct rga2_req * msg)769 static void RGA2_set_reg_rop_info(u8 *base, struct rga2_req *msg)
770 {
771 RK_U32 *bRGA_ALPHA_CTRL0;
772 RK_U32 *bRGA_ROP_CTRL0;
773 RK_U32 *bRGA_ROP_CTRL1;
774 RK_U32 *bRGA_MASK_ADDR;
775 RK_U32 *bRGA_FG_COLOR;
776 RK_U32 *bRGA_PAT_CON;
777
778 RK_U32 rop_code0 = 0;
779 RK_U32 rop_code1 = 0;
780
781 bRGA_ALPHA_CTRL0 = (RK_U32 *)(base + RGA2_ALPHA_CTRL0_OFFSET);
782 bRGA_ROP_CTRL0 = (RK_U32 *)(base + RGA2_ROP_CTRL0_OFFSET);
783 bRGA_ROP_CTRL1 = (RK_U32 *)(base + RGA2_ROP_CTRL1_OFFSET);
784 bRGA_MASK_ADDR = (RK_U32 *)(base + RGA2_MASK_BASE_OFFSET);
785 bRGA_FG_COLOR = (RK_U32 *)(base + RGA2_SRC_FG_COLOR_OFFSET);
786 bRGA_PAT_CON = (RK_U32 *)(base + RGA2_PAT_CON_OFFSET);
787
788 if(msg->rop_mode == 0) {
789 rop_code0 = RGA2_ROP3_code[(msg->rop_code & 0xff)];
790 }
791 else if(msg->rop_mode == 1) {
792 rop_code0 = RGA2_ROP3_code[(msg->rop_code & 0xff)];
793 }
794 else if(msg->rop_mode == 2) {
795 rop_code0 = RGA2_ROP3_code[(msg->rop_code & 0xff)];
796 rop_code1 = RGA2_ROP3_code[(msg->rop_code & 0xff00)>>8];
797 }
798
799 *bRGA_ROP_CTRL0 = rop_code0;
800 *bRGA_ROP_CTRL1 = rop_code1;
801 *bRGA_FG_COLOR = msg->fg_color;
802 *bRGA_MASK_ADDR = (RK_U32)msg->rop_mask_addr;
803 *bRGA_PAT_CON = (msg->pat.act_w-1) | ((msg->pat.act_h-1) << 8)
804 | (msg->pat.x_offset << 16) | (msg->pat.y_offset << 24);
805 *bRGA_ALPHA_CTRL0 = *bRGA_ALPHA_CTRL0 | (((msg->endian_mode >> 1) & 1) << 20);
806
807 }
808
RGA2_set_reg_full_csc(u8 * base,struct rga2_req * msg)809 static void RGA2_set_reg_full_csc(u8 *base, struct rga2_req *msg)
810 {
811 RK_U32 *bRGA2_DST_CSC_00;
812 RK_U32 *bRGA2_DST_CSC_01;
813 RK_U32 *bRGA2_DST_CSC_02;
814 RK_U32 *bRGA2_DST_CSC_OFF0;
815
816 RK_U32 *bRGA2_DST_CSC_10;
817 RK_U32 *bRGA2_DST_CSC_11;
818 RK_U32 *bRGA2_DST_CSC_12;
819 RK_U32 *bRGA2_DST_CSC_OFF1;
820
821 RK_U32 *bRGA2_DST_CSC_20;
822 RK_U32 *bRGA2_DST_CSC_21;
823 RK_U32 *bRGA2_DST_CSC_22;
824 RK_U32 *bRGA2_DST_CSC_OFF2;
825
826 bRGA2_DST_CSC_00 = (RK_U32 *)(base + RGA2_DST_CSC_00_OFFSET);
827 bRGA2_DST_CSC_01 = (RK_U32 *)(base + RGA2_DST_CSC_01_OFFSET);
828 bRGA2_DST_CSC_02 = (RK_U32 *)(base + RGA2_DST_CSC_02_OFFSET);
829 bRGA2_DST_CSC_OFF0 = (RK_U32 *)(base + RGA2_DST_CSC_OFF0_OFFSET);
830
831 bRGA2_DST_CSC_10 = (RK_U32 *)(base + RGA2_DST_CSC_10_OFFSET);
832 bRGA2_DST_CSC_11 = (RK_U32 *)(base + RGA2_DST_CSC_11_OFFSET);
833 bRGA2_DST_CSC_12 = (RK_U32 *)(base + RGA2_DST_CSC_12_OFFSET);
834 bRGA2_DST_CSC_OFF1 = (RK_U32 *)(base + RGA2_DST_CSC_OFF1_OFFSET);
835
836 bRGA2_DST_CSC_20 = (RK_U32 *)(base + RGA2_DST_CSC_20_OFFSET);
837 bRGA2_DST_CSC_21 = (RK_U32 *)(base + RGA2_DST_CSC_21_OFFSET);
838 bRGA2_DST_CSC_22 = (RK_U32 *)(base + RGA2_DST_CSC_22_OFFSET);
839 bRGA2_DST_CSC_OFF2 = (RK_U32 *)(base + RGA2_DST_CSC_OFF2_OFFSET);
840
841 /* full csc coefficient */
842 /* Y coefficient */
843 *bRGA2_DST_CSC_00 = msg->full_csc.coe_y.r_v;
844 *bRGA2_DST_CSC_01 = msg->full_csc.coe_y.g_y;
845 *bRGA2_DST_CSC_02 = msg->full_csc.coe_y.b_u;
846 *bRGA2_DST_CSC_OFF0 = msg->full_csc.coe_y.off;
847 /* U coefficient */
848 *bRGA2_DST_CSC_10 = msg->full_csc.coe_u.r_v;
849 *bRGA2_DST_CSC_11 = msg->full_csc.coe_u.g_y;
850 *bRGA2_DST_CSC_12 = msg->full_csc.coe_u.b_u;
851 *bRGA2_DST_CSC_OFF1 = msg->full_csc.coe_u.off;
852 /* V coefficient */
853 *bRGA2_DST_CSC_20 = msg->full_csc.coe_v.r_v;
854 *bRGA2_DST_CSC_21 = msg->full_csc.coe_v.g_y;
855 *bRGA2_DST_CSC_22 = msg->full_csc.coe_v.b_u;
856 *bRGA2_DST_CSC_OFF2 = msg->full_csc.coe_v.off;
857 }
858
RGA2_set_reg_color_palette(RK_U8 * base,struct rga2_req * msg)859 static void RGA2_set_reg_color_palette(RK_U8 *base, struct rga2_req *msg)
860 {
861 RK_U32 *bRGA_SRC_BASE0, *bRGA_SRC_INFO, *bRGA_SRC_VIR_INFO, *bRGA_SRC_ACT_INFO, *bRGA_SRC_FG_COLOR, *bRGA_SRC_BG_COLOR;
862 RK_U32 *p;
863 RK_S16 x_off, y_off;
864 RK_U16 src_stride;
865 RK_U8 shift;
866 RK_U32 sw;
867 RK_U32 byte_num;
868 RK_U32 reg;
869
870 bRGA_SRC_BASE0 = (RK_U32 *)(base + RGA2_SRC_BASE0_OFFSET);
871 bRGA_SRC_INFO = (RK_U32 *)(base + RGA2_SRC_INFO_OFFSET);
872 bRGA_SRC_VIR_INFO = (RK_U32 *)(base + RGA2_SRC_VIR_INFO_OFFSET);
873 bRGA_SRC_ACT_INFO = (RK_U32 *)(base + RGA2_SRC_ACT_INFO_OFFSET);
874 bRGA_SRC_FG_COLOR = (RK_U32 *)(base + RGA2_SRC_FG_COLOR_OFFSET);
875 bRGA_SRC_BG_COLOR = (RK_U32 *)(base + RGA2_SRC_BG_COLOR_OFFSET);
876
877 reg = 0;
878
879 shift = 3 - msg->palette_mode;
880
881 x_off = msg->src.x_offset;
882 y_off = msg->src.y_offset;
883
884 sw = msg->src.vir_w;
885 byte_num = sw >> shift;
886
887 src_stride = (byte_num + 3) & (~3);
888
889 p = (RK_U32 *)((unsigned long)msg->src.yrgb_addr);
890
891 #if 0
892 if(endian_mode)
893 {
894 p = p + (x_off>>shift) + y_off*src_stride;
895 }
896 else
897 {
898 p = p + (((x_off>>shift)>>2)<<2) + (3 - ((x_off>>shift) & 3)) + y_off*src_stride;
899 }
900 #endif
901
902 p = p + (x_off>>shift) + y_off*src_stride;
903
904
905 *bRGA_SRC_BASE0 = (unsigned long)p;
906
907 reg = ((reg & (~m_RGA2_SRC_INFO_SW_SRC_FMT)) | (s_RGA2_SRC_INFO_SW_SRC_FMT((msg->palette_mode | 0xc))));
908 reg = ((reg & (~m_RGA2_SRC_INFO_SW_SW_CP_ENDAIN)) | (s_RGA2_SRC_INFO_SW_SW_CP_ENDAIN(msg->endian_mode & 1)));
909 *bRGA_SRC_VIR_INFO = src_stride >> 2;
910 *bRGA_SRC_ACT_INFO = (msg->src.act_w - 1) | ((msg->src.act_h - 1) << 16);
911 *bRGA_SRC_INFO = reg;
912
913 *bRGA_SRC_FG_COLOR = msg->fg_color;
914 *bRGA_SRC_BG_COLOR = msg->bg_color;
915
916 }
917
RGA2_set_reg_color_fill(u8 * base,struct rga2_req * msg)918 static void RGA2_set_reg_color_fill(u8 *base, struct rga2_req *msg)
919 {
920 RK_U32 *bRGA_CF_GR_A;
921 RK_U32 *bRGA_CF_GR_B;
922 RK_U32 *bRGA_CF_GR_G;
923 RK_U32 *bRGA_CF_GR_R;
924 RK_U32 *bRGA_SRC_FG_COLOR;
925 RK_U32 *bRGA_MASK_ADDR;
926 RK_U32 *bRGA_PAT_CON;
927
928 RK_U32 mask_stride;
929 RK_U32 *bRGA_SRC_VIR_INFO;
930
931 bRGA_SRC_FG_COLOR = (RK_U32 *)(base + RGA2_SRC_FG_COLOR_OFFSET);
932
933 bRGA_CF_GR_A = (RK_U32 *)(base + RGA2_CF_GR_A_OFFSET);
934 bRGA_CF_GR_B = (RK_U32 *)(base + RGA2_CF_GR_B_OFFSET);
935 bRGA_CF_GR_G = (RK_U32 *)(base + RGA2_CF_GR_G_OFFSET);
936 bRGA_CF_GR_R = (RK_U32 *)(base + RGA2_CF_GR_R_OFFSET);
937
938 bRGA_MASK_ADDR = (RK_U32 *)(base + RGA2_MASK_BASE_OFFSET);
939 bRGA_PAT_CON = (RK_U32 *)(base + RGA2_PAT_CON_OFFSET);
940
941 bRGA_SRC_VIR_INFO = (RK_U32 *)(base + RGA2_SRC_VIR_INFO_OFFSET);
942
943 mask_stride = msg->rop_mask_stride;
944
945 if(msg->color_fill_mode == 0)
946 {
947 /* solid color */
948 *bRGA_CF_GR_A = (msg->gr_color.gr_x_a & 0xffff) | (msg->gr_color.gr_y_a << 16);
949 *bRGA_CF_GR_B = (msg->gr_color.gr_x_b & 0xffff) | (msg->gr_color.gr_y_b << 16);
950 *bRGA_CF_GR_G = (msg->gr_color.gr_x_g & 0xffff) | (msg->gr_color.gr_y_g << 16);
951 *bRGA_CF_GR_R = (msg->gr_color.gr_x_r & 0xffff) | (msg->gr_color.gr_y_r << 16);
952
953 *bRGA_SRC_FG_COLOR = msg->fg_color;
954 }
955 else
956 {
957 /* patten color */
958 *bRGA_MASK_ADDR = (RK_U32)msg->pat.yrgb_addr;
959 *bRGA_PAT_CON = (msg->pat.act_w - 1) | ((msg->pat.act_h - 1) << 8)
960 | (msg->pat.x_offset << 16) | (msg->pat.y_offset << 24);
961 }
962 *bRGA_SRC_VIR_INFO = mask_stride << 16;
963 }
964
RGA2_set_reg_update_palette_table(RK_U8 * base,struct rga2_req * msg)965 static void RGA2_set_reg_update_palette_table(RK_U8 *base, struct rga2_req *msg)
966 {
967 RK_U32 *bRGA_MASK_BASE;
968 RK_U32 *bRGA_FADING_CTRL;
969
970 bRGA_MASK_BASE = (RK_U32 *)(base + RGA2_MASK_BASE_OFFSET);
971 bRGA_FADING_CTRL = (RK_U32 *)(base + RGA2_FADING_CTRL_OFFSET);
972
973 *bRGA_FADING_CTRL = msg->fading_g_value << 8;
974 *bRGA_MASK_BASE = (RK_U32)msg->pat.yrgb_addr;
975 }
976
977
RGA2_set_reg_update_patten_buff(RK_U8 * base,struct rga2_req * msg)978 static void RGA2_set_reg_update_patten_buff(RK_U8 *base, struct rga2_req *msg)
979 {
980 u32 *bRGA_PAT_MST;
981 u32 *bRGA_PAT_CON;
982 u32 *bRGA_PAT_START_POINT;
983 RK_U32 *bRGA_FADING_CTRL;
984 u32 reg = 0;
985 rga_img_info_t *pat;
986
987 RK_U32 num, offset;
988
989 pat = &msg->pat;
990
991 num = (pat->act_w * pat->act_h) - 1;
992
993 offset = pat->act_w * pat->y_offset + pat->x_offset;
994
995 bRGA_PAT_START_POINT = (RK_U32 *)(base + RGA2_FADING_CTRL_OFFSET);
996 bRGA_PAT_MST = (RK_U32 *)(base + RGA2_MASK_BASE_OFFSET);
997 bRGA_PAT_CON = (RK_U32 *)(base + RGA2_PAT_CON_OFFSET);
998 bRGA_FADING_CTRL = (RK_U32 *)(base + RGA2_FADING_CTRL_OFFSET);
999
1000 *bRGA_PAT_MST = (RK_U32)msg->pat.yrgb_addr;
1001 *bRGA_PAT_START_POINT = (pat->act_w * pat->y_offset) + pat->x_offset;
1002
1003 reg = (pat->act_w-1) | ((pat->act_h-1) << 8) | (pat->x_offset << 16) | (pat->y_offset << 24);
1004 *bRGA_PAT_CON = reg;
1005
1006 *bRGA_FADING_CTRL = (num << 8) | offset;
1007 }
1008
RGA2_set_pat_info(RK_U8 * base,struct rga2_req * msg)1009 static void RGA2_set_pat_info(RK_U8 *base, struct rga2_req *msg)
1010 {
1011 u32 *bRGA_PAT_CON;
1012 u32 *bRGA_FADING_CTRL;
1013 u32 reg = 0;
1014 rga_img_info_t *pat;
1015
1016 RK_U32 num, offset;
1017
1018 pat = &msg->pat;
1019
1020 num = ((pat->act_w * pat->act_h) - 1) & 0xff;
1021
1022 offset = (pat->act_w * pat->y_offset) + pat->x_offset;
1023
1024 bRGA_PAT_CON = (RK_U32 *)(base + RGA2_PAT_CON_OFFSET);
1025 bRGA_FADING_CTRL = (RK_U32 *)(base + RGA2_FADING_CTRL_OFFSET);
1026
1027 reg = (pat->act_w-1) | ((pat->act_h-1) << 8) | (pat->x_offset << 16) | (pat->y_offset << 24);
1028 *bRGA_PAT_CON = reg;
1029 *bRGA_FADING_CTRL = (num << 8) | offset;
1030 }
1031
RGA2_set_mmu_info(RK_U8 * base,struct rga2_req * msg)1032 static void RGA2_set_mmu_info(RK_U8 *base, struct rga2_req *msg)
1033 {
1034 RK_U32 *bRGA_MMU_CTRL1;
1035 RK_U32 *bRGA_MMU_SRC_BASE;
1036 RK_U32 *bRGA_MMU_SRC1_BASE;
1037 RK_U32 *bRGA_MMU_DST_BASE;
1038 RK_U32 *bRGA_MMU_ELS_BASE;
1039
1040 RK_U32 reg;
1041
1042 bRGA_MMU_CTRL1 = (RK_U32 *)(base + RGA2_MMU_CTRL1_OFFSET);
1043 bRGA_MMU_SRC_BASE = (RK_U32 *)(base + RGA2_MMU_SRC_BASE_OFFSET);
1044 bRGA_MMU_SRC1_BASE = (RK_U32 *)(base + RGA2_MMU_SRC1_BASE_OFFSET);
1045 bRGA_MMU_DST_BASE = (RK_U32 *)(base + RGA2_MMU_DST_BASE_OFFSET);
1046 bRGA_MMU_ELS_BASE = (RK_U32 *)(base + RGA2_MMU_ELS_BASE_OFFSET);
1047
1048 reg = (msg->mmu_info.src0_mmu_flag & 0xf) | ((msg->mmu_info.src1_mmu_flag & 0xf) << 4)
1049 | ((msg->mmu_info.dst_mmu_flag & 0xf) << 8) | ((msg->mmu_info.els_mmu_flag & 0x3) << 12);
1050
1051 *bRGA_MMU_CTRL1 = reg;
1052 *bRGA_MMU_SRC_BASE = (RK_U32)(msg->mmu_info.src0_base_addr) >> 4;
1053 *bRGA_MMU_SRC1_BASE = (RK_U32)(msg->mmu_info.src1_base_addr) >> 4;
1054 *bRGA_MMU_DST_BASE = (RK_U32)(msg->mmu_info.dst_base_addr) >> 4;
1055 *bRGA_MMU_ELS_BASE = (RK_U32)(msg->mmu_info.els_base_addr) >> 4;
1056 }
1057
1058 int
RGA2_gen_reg_info(RK_U8 * base,RK_U8 * csc_base,struct rga2_req * msg)1059 RGA2_gen_reg_info(RK_U8 *base, RK_U8 *csc_base, struct rga2_req *msg)
1060 {
1061 RK_U8 dst_nn_quantize_en = 0;
1062
1063 RGA2_set_mode_ctrl(base, msg);
1064
1065 RGA2_set_pat_info(base, msg);
1066
1067 switch(msg->render_mode)
1068 {
1069 case bitblt_mode:
1070 RGA2_set_reg_src_info(base, msg);
1071 RGA2_set_reg_dst_info(base, msg);
1072 dst_nn_quantize_en = (msg->alpha_rop_flag >> 8)&0x1 ;
1073 if (dst_nn_quantize_en != 1) {
1074 if ((msg->dst.format != RGA2_FORMAT_Y4)) {
1075 RGA2_set_reg_alpha_info(base, msg);
1076 RGA2_set_reg_rop_info(base, msg);
1077 }
1078 }
1079
1080 if (msg->full_csc.flag) {
1081 RGA2_set_reg_full_csc(csc_base, msg);
1082 }
1083 break;
1084 case color_fill_mode :
1085 RGA2_set_reg_color_fill(base, msg);
1086 RGA2_set_reg_dst_info(base, msg);
1087 RGA2_set_reg_alpha_info(base, msg);
1088 break;
1089 case color_palette_mode :
1090 RGA2_set_reg_color_palette(base, msg);
1091 RGA2_set_reg_dst_info(base, msg);
1092 break;
1093 case update_palette_table_mode :
1094 RGA2_set_reg_update_palette_table(base, msg);
1095 break;
1096 case update_patten_buff_mode :
1097 RGA2_set_reg_update_patten_buff(base, msg);
1098 break;
1099 default :
1100 printk("RGA2 ERROR msg render mode %d \n", msg->render_mode);
1101 break;
1102
1103 }
1104
1105 RGA2_set_mmu_info(base, msg);
1106
1107 return 0;
1108
1109 }
1110
format_name_convert(uint32_t * df,uint32_t sf)1111 static void format_name_convert(uint32_t *df, uint32_t sf)
1112 {
1113 switch(sf)
1114 {
1115 case 0x0: *df = RGA2_FORMAT_RGBA_8888; break;
1116 case 0x1: *df = RGA2_FORMAT_RGBX_8888; break;
1117 case 0x2: *df = RGA2_FORMAT_RGB_888; break;
1118 case 0x3: *df = RGA2_FORMAT_BGRA_8888; break;
1119 case 0x4: *df = RGA2_FORMAT_RGB_565; break;
1120 case 0x5: *df = RGA2_FORMAT_RGBA_5551; break;
1121 case 0x6: *df = RGA2_FORMAT_RGBA_4444; break;
1122 case 0x7: *df = RGA2_FORMAT_BGR_888; break;
1123 case 0x16: *df = RGA2_FORMAT_BGRX_8888; break;
1124 case 0x8: *df = RGA2_FORMAT_YCbCr_422_SP; break;
1125 case 0x9: *df = RGA2_FORMAT_YCbCr_422_P; break;
1126 case 0xa: *df = RGA2_FORMAT_YCbCr_420_SP; break;
1127 case 0xb: *df = RGA2_FORMAT_YCbCr_420_P; break;
1128 case 0xc: *df = RGA2_FORMAT_YCrCb_422_SP; break;
1129 case 0xd: *df = RGA2_FORMAT_YCrCb_422_P; break;
1130 case 0xe: *df = RGA2_FORMAT_YCrCb_420_SP; break;
1131 case 0xf: *df = RGA2_FORMAT_YCrCb_420_P; break;
1132
1133 case 0x10: *df = RGA2_FORMAT_BPP_1; break;
1134 case 0x11: *df = RGA2_FORMAT_BPP_2; break;
1135 case 0x12: *df = RGA2_FORMAT_BPP_4; break;
1136 case 0x13: *df = RGA2_FORMAT_BPP_8; break;
1137
1138 case 0x14: *df = RGA2_FORMAT_Y4; break;
1139 case 0x15: *df = RGA2_FORMAT_YCbCr_400; break;
1140
1141 case 0x18: *df = RGA2_FORMAT_YVYU_422; break;
1142 case 0x19: *df = RGA2_FORMAT_YVYU_420; break;
1143 case 0x1a: *df = RGA2_FORMAT_VYUY_422; break;
1144 case 0x1b: *df = RGA2_FORMAT_VYUY_420; break;
1145 case 0x1c: *df = RGA2_FORMAT_YUYV_422; break;
1146 case 0x1d: *df = RGA2_FORMAT_YUYV_420; break;
1147 case 0x1e: *df = RGA2_FORMAT_UYVY_422; break;
1148 case 0x1f: *df = RGA2_FORMAT_UYVY_420; break;
1149
1150 case 0x20:*df = RGA2_FORMAT_YCbCr_420_SP_10B; break;
1151 case 0x21:*df = RGA2_FORMAT_YCrCb_420_SP_10B; break;
1152 case 0x22:*df = RGA2_FORMAT_YCbCr_422_SP_10B; break;
1153 case 0x23:*df = RGA2_FORMAT_YCrCb_422_SP_10B; break;
1154
1155 case 0x24:*df = RGA2_FORMAT_BGR_565; break;
1156 case 0x25:*df = RGA2_FORMAT_BGRA_5551; break;
1157 case 0x26:*df = RGA2_FORMAT_BGRA_4444; break;
1158
1159
1160 case 0x28 : *df = RGA2_FORMAT_ARGB_8888; break;
1161 case 0x29 : *df = RGA2_FORMAT_XRGB_8888; break;
1162 case 0x2a : *df = RGA2_FORMAT_ARGB_5551; break;
1163 case 0x2b : *df = RGA2_FORMAT_ARGB_4444; break;
1164 case 0x2c : *df = RGA2_FORMAT_ABGR_8888; break;
1165 case 0x2d : *df = RGA2_FORMAT_XBGR_8888; break;
1166 case 0x2e : *df = RGA2_FORMAT_ABGR_5551; break;
1167 case 0x2f : *df = RGA2_FORMAT_ABGR_4444; break;
1168 }
1169 }
1170
RGA_MSG_2_RGA2_MSG(struct rga_req * req_rga,struct rga2_req * req)1171 void RGA_MSG_2_RGA2_MSG(struct rga_req *req_rga, struct rga2_req *req)
1172 {
1173 u16 alpha_mode_0, alpha_mode_1;
1174 #if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 4, 0))
1175 if (req_rga->render_mode & RGA_BUF_GEM_TYPE_MASK)
1176 req->buf_type = RGA_BUF_GEM_TYPE_MASK & RGA_BUF_GEM_TYPE_DMA;
1177
1178 req_rga->render_mode &= (~RGA_BUF_GEM_TYPE_MASK);
1179 #endif
1180
1181 if (req_rga->render_mode == 6)
1182 req->render_mode = update_palette_table_mode;
1183 else if (req_rga->render_mode == 7)
1184 req->render_mode = update_patten_buff_mode;
1185 else if (req_rga->render_mode == 5)
1186 req->render_mode = bitblt_mode;
1187 else
1188 req->render_mode = req_rga->render_mode;
1189
1190 memcpy(&req->src, &req_rga->src, sizeof(req_rga->src));
1191 memcpy(&req->dst, &req_rga->dst, sizeof(req_rga->dst));
1192 /* The application will only import pat or src1. */
1193 if (req->render_mode == update_palette_table_mode) {
1194 memcpy(&req->pat, &req_rga->pat, sizeof(req_rga->pat));
1195 } else {
1196 memcpy(&req->src1, &req_rga->pat, sizeof(req_rga->pat));
1197 }
1198
1199 format_name_convert(&req->src.format, req_rga->src.format);
1200 format_name_convert(&req->dst.format, req_rga->dst.format);
1201 format_name_convert(&req->src1.format, req_rga->pat.format);
1202
1203 switch (req_rga->rotate_mode & 0x0F) {
1204 case 1:
1205 if(req_rga->sina == 0 && req_rga->cosa == 65536) {
1206 /* rotate 0 */
1207 req->rotate_mode = 0;
1208 } else if (req_rga->sina == 65536 && req_rga->cosa == 0) {
1209 /* rotate 90 */
1210 req->rotate_mode = 1;
1211 req->dst.x_offset = req_rga->dst.x_offset - req_rga->dst.act_h + 1;
1212 req->dst.act_w = req_rga->dst.act_h;
1213 req->dst.act_h = req_rga->dst.act_w;
1214 } else if (req_rga->sina == 0 && req_rga->cosa == -65536) {
1215 /* rotate 180 */
1216 req->rotate_mode = 2;
1217 req->dst.x_offset = req_rga->dst.x_offset - req_rga->dst.act_w + 1;
1218 req->dst.y_offset = req_rga->dst.y_offset - req_rga->dst.act_h + 1;
1219 } else if (req_rga->sina == -65536 && req_rga->cosa == 0) {
1220 /* totate 270 */
1221 req->rotate_mode = 3;
1222 req->dst.y_offset = req_rga->dst.y_offset - req_rga->dst.act_w + 1;
1223 req->dst.act_w = req_rga->dst.act_h;
1224 req->dst.act_h = req_rga->dst.act_w;
1225 }
1226 break;
1227 case 2:
1228 //x_mirror
1229 req->rotate_mode |= (1 << 4);
1230 break;
1231 case 3:
1232 //y_mirror
1233 req->rotate_mode |= (2 << 4);
1234 break;
1235 case 4:
1236 //x_mirror+y_mirror
1237 req->rotate_mode |= (3 << 4);
1238 break;
1239 default:
1240 req->rotate_mode = 0;
1241 break;
1242 }
1243
1244 switch ((req_rga->rotate_mode & 0xF0) >> 4) {
1245 case 2:
1246 //x_mirror
1247 req->rotate_mode |= (1 << 4);
1248 break;
1249 case 3:
1250 //y_mirror
1251 req->rotate_mode |= (2 << 4);
1252 break;
1253 case 4:
1254 //x_mirror+y_mirror
1255 req->rotate_mode |= (3 << 4);
1256 break;
1257 }
1258
1259 if((req->dst.act_w > 2048) && (req->src.act_h < req->dst.act_h))
1260 req->scale_bicu_mode |= (1<<4);
1261
1262 req->LUT_addr = req_rga->LUT_addr;
1263 req->rop_mask_addr = req_rga->rop_mask_addr;
1264
1265 req->bitblt_mode = req_rga->bsfilter_flag;
1266
1267 req->src_a_global_val = req_rga->alpha_global_value;
1268 req->dst_a_global_val = req_rga->alpha_global_value;
1269 req->rop_code = req_rga->rop_code;
1270 req->rop_mode = req_rga->alpha_rop_mode;
1271
1272 req->color_fill_mode = req_rga->color_fill_mode;
1273 req->alpha_zero_key = req_rga->alpha_rop_mode >> 4;
1274 req->src_trans_mode = req_rga->src_trans_mode;
1275 req->color_key_min = req_rga->color_key_min;
1276 req->color_key_max = req_rga->color_key_max;
1277
1278 req->fg_color = req_rga->fg_color;
1279 req->bg_color = req_rga->bg_color;
1280 memcpy(&req->gr_color, &req_rga->gr_color, sizeof(req_rga->gr_color));
1281 memcpy(&req->full_csc, &req_rga->full_csc, sizeof(req_rga->full_csc));
1282
1283 req->palette_mode = req_rga->palette_mode;
1284 req->yuv2rgb_mode = req_rga->yuv2rgb_mode;
1285 req->endian_mode = req_rga->endian_mode;
1286 req->rgb2yuv_mode = 0;
1287
1288 req->fading_alpha_value = 0;
1289 req->fading_r_value = req_rga->fading.r;
1290 req->fading_g_value = req_rga->fading.g;
1291 req->fading_b_value = req_rga->fading.b;
1292
1293 /* alpha mode set */
1294 req->alpha_rop_flag = 0;
1295 req->alpha_rop_flag |= (((req_rga->alpha_rop_flag & 1))); // alpha_rop_enable
1296 req->alpha_rop_flag |= (((req_rga->alpha_rop_flag >> 1) & 1) << 1); // rop_enable
1297 req->alpha_rop_flag |= (((req_rga->alpha_rop_flag >> 2) & 1) << 2); // fading_enable
1298 req->alpha_rop_flag |= (((req_rga->alpha_rop_flag >> 4) & 1) << 3); // alpha_cal_mode_sel
1299 req->alpha_rop_flag |= (((req_rga->alpha_rop_flag >> 5) & 1) << 6); // dst_dither_down
1300 req->alpha_rop_flag |= (((req_rga->alpha_rop_flag >> 6) & 1) << 7); // gradient fill mode sel
1301
1302 req->alpha_rop_flag |= (((req_rga->alpha_rop_flag >> 8) & 1) << 8); // nn_quantize
1303 req->dither_mode = req_rga->dither_mode;
1304
1305 if (((req_rga->alpha_rop_flag) & 1)) {
1306 if ((req_rga->alpha_rop_flag >> 3) & 1) {
1307 /* porter duff alpha enable */
1308 switch (req_rga->PD_mode)
1309 {
1310 case 0: //dst = 0
1311 break;
1312 case 1: //dst = src
1313 req->alpha_mode_0 = 0x0212;
1314 req->alpha_mode_1 = 0x0212;
1315 break;
1316 case 2: //dst = dst
1317 req->alpha_mode_0 = 0x1202;
1318 req->alpha_mode_1 = 0x1202;
1319 break;
1320 case 3: //dst = (256*sc + (256 - sa)*dc) >> 8
1321 if((req_rga->alpha_rop_mode & 3) == 0) {
1322 /* both use globalAlpha. */
1323 alpha_mode_0 = 0x3010;
1324 alpha_mode_1 = 0x3010;
1325 }
1326 else if ((req_rga->alpha_rop_mode & 3) == 1) {
1327 /* Do not use globalAlpha. */
1328 alpha_mode_0 = 0x3212;
1329 alpha_mode_1 = 0x3212;
1330 }
1331 else if ((req_rga->alpha_rop_mode & 3) == 2) {
1332 /* dst use globalAlpha, and dst has pixelAlpha. */
1333 alpha_mode_0 = 0x3014;
1334 alpha_mode_1 = 0x3014;
1335 }
1336 else {
1337 /* dst use globalAlpha, and dst does not have pixelAlpha. */
1338 alpha_mode_0 = 0x3012;
1339 alpha_mode_1 = 0x3012;
1340 }
1341 req->alpha_mode_0 = alpha_mode_0;
1342 req->alpha_mode_1 = alpha_mode_1;
1343 break;
1344 case 4: //dst = (sc*(256-da) + 256*dc) >> 8
1345 /* Do not use globalAlpha. */
1346 req->alpha_mode_0 = 0x1232;
1347 req->alpha_mode_1 = 0x1232;
1348 break;
1349 case 5: //dst = (da*sc) >> 8
1350 break;
1351 case 6: //dst = (sa*dc) >> 8
1352 break;
1353 case 7: //dst = ((256-da)*sc) >> 8
1354 break;
1355 case 8: //dst = ((256-sa)*dc) >> 8
1356 break;
1357 case 9: //dst = (da*sc + (256-sa)*dc) >> 8
1358 req->alpha_mode_0 = 0x3040;
1359 req->alpha_mode_1 = 0x3040;
1360 break;
1361 case 10://dst = ((256-da)*sc + (sa*dc)) >> 8
1362 break;
1363 case 11://dst = ((256-da)*sc + (256-sa)*dc) >> 8;
1364 break;
1365 case 12:
1366 req->alpha_mode_0 = 0x0010;
1367 req->alpha_mode_1 = 0x0820;
1368 break;
1369 default:
1370 break;
1371 }
1372 /* Real color mode */
1373 if ((req_rga->alpha_rop_flag >> 9) & 1) {
1374 if (req->alpha_mode_0 & (0x01 << 1))
1375 req->alpha_mode_0 |= (1 << 7);
1376 if (req->alpha_mode_0 & (0x01 << 9))
1377 req->alpha_mode_0 |= (1 << 15);
1378 }
1379 }
1380 else {
1381 if((req_rga->alpha_rop_mode & 3) == 0) {
1382 req->alpha_mode_0 = 0x3040;
1383 req->alpha_mode_1 = 0x3040;
1384 }
1385 else if ((req_rga->alpha_rop_mode & 3) == 1) {
1386 req->alpha_mode_0 = 0x3042;
1387 req->alpha_mode_1 = 0x3242;
1388 }
1389 else if ((req_rga->alpha_rop_mode & 3) == 2) {
1390 req->alpha_mode_0 = 0x3044;
1391 req->alpha_mode_1 = 0x3044;
1392 }
1393 }
1394 }
1395
1396 if (req_rga->mmu_info.mmu_en && (req_rga->mmu_info.mmu_flag & 1) == 1) {
1397 req->mmu_info.src0_mmu_flag = 1;
1398 req->mmu_info.dst_mmu_flag = 1;
1399
1400 if (req_rga->mmu_info.mmu_flag >> 31) {
1401 req->mmu_info.src0_mmu_flag = ((req_rga->mmu_info.mmu_flag >> 8) & 1);
1402 req->mmu_info.src1_mmu_flag = ((req_rga->mmu_info.mmu_flag >> 9) & 1);
1403 req->mmu_info.dst_mmu_flag = ((req_rga->mmu_info.mmu_flag >> 10) & 1);
1404 req->mmu_info.els_mmu_flag = ((req_rga->mmu_info.mmu_flag >> 11) & 1);
1405 }
1406 else {
1407 if (req_rga->src.yrgb_addr >= 0xa0000000) {
1408 req->mmu_info.src0_mmu_flag = 0;
1409 req->src.yrgb_addr = req_rga->src.yrgb_addr - 0x60000000;
1410 req->src.uv_addr = req_rga->src.uv_addr - 0x60000000;
1411 req->src.v_addr = req_rga->src.v_addr - 0x60000000;
1412 }
1413
1414 if (req_rga->dst.yrgb_addr >= 0xa0000000) {
1415 req->mmu_info.dst_mmu_flag = 0;
1416 req->dst.yrgb_addr = req_rga->dst.yrgb_addr - 0x60000000;
1417 }
1418
1419 if (req_rga->pat.yrgb_addr >= 0xa0000000) {
1420 req->mmu_info.src1_mmu_flag = 0;
1421 req->src1.yrgb_addr = req_rga->pat.yrgb_addr - 0x60000000;
1422 }
1423 }
1424 }
1425 }
1426
memcpy_img_info(struct rga_img_info_t * dst,struct rga_img_info_32_t * src)1427 static void memcpy_img_info(struct rga_img_info_t *dst, struct rga_img_info_32_t *src)
1428 {
1429 dst->yrgb_addr = src->yrgb_addr; /* yrgb mem addr */
1430 dst->uv_addr = src->uv_addr; /* cb/cr mem addr */
1431 dst->v_addr = src->v_addr; /* cr mem addr */
1432 dst->format = src->format; //definition by RK_FORMAT
1433
1434 dst->act_w = src->act_w;
1435 dst->act_h = src->act_h;
1436 dst->x_offset = src->x_offset;
1437 dst->y_offset = src->y_offset;
1438
1439 dst->vir_w = src->vir_w;
1440 dst->vir_h = src->vir_h;
1441 dst->endian_mode = src->endian_mode; //for BPP
1442 dst->alpha_swap = src->alpha_swap;
1443 }
1444
RGA_MSG_2_RGA2_MSG_32(struct rga_req_32 * req_rga,struct rga2_req * req)1445 void RGA_MSG_2_RGA2_MSG_32(struct rga_req_32 *req_rga, struct rga2_req *req)
1446 {
1447 u16 alpha_mode_0, alpha_mode_1;
1448 #if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 4, 0))
1449 if (req_rga->render_mode & RGA_BUF_GEM_TYPE_MASK)
1450 req->buf_type = RGA_BUF_GEM_TYPE_MASK & RGA_BUF_GEM_TYPE_DMA;
1451
1452 req_rga->render_mode &= (~RGA_BUF_GEM_TYPE_MASK);
1453 #endif
1454 if (req_rga->render_mode == 6)
1455 req->render_mode = update_palette_table_mode;
1456 else if (req_rga->render_mode == 7)
1457 req->render_mode = update_patten_buff_mode;
1458 else if (req_rga->render_mode == 5)
1459 req->render_mode = bitblt_mode;
1460 else
1461 req->render_mode = req_rga->render_mode;
1462 memcpy_img_info(&req->src, &req_rga->src);
1463 memcpy_img_info(&req->dst, &req_rga->dst);
1464 /* The application will only import pat or src1. */
1465 if (req->render_mode == update_palette_table_mode) {
1466 memcpy_img_info(&req->pat, &req_rga->pat);
1467 } else {
1468 memcpy_img_info(&req->src1,&req_rga->pat);
1469 }
1470 format_name_convert(&req->src.format, req_rga->src.format);
1471 format_name_convert(&req->dst.format, req_rga->dst.format);
1472 format_name_convert(&req->src1.format, req_rga->pat.format);
1473
1474 switch (req_rga->rotate_mode & 0x0F) {
1475 case 1:
1476 if(req_rga->sina == 0 && req_rga->cosa == 65536) {
1477 /* rotate 0 */
1478 req->rotate_mode = 0;
1479 } else if (req_rga->sina == 65536 && req_rga->cosa == 0) {
1480 /* rotate 90 */
1481 req->rotate_mode = 1;
1482 req->dst.x_offset = req_rga->dst.x_offset - req_rga->dst.act_h + 1;
1483 req->dst.act_w = req_rga->dst.act_h;
1484 req->dst.act_h = req_rga->dst.act_w;
1485 } else if (req_rga->sina == 0 && req_rga->cosa == -65536) {
1486 /* rotate 180 */
1487 req->rotate_mode = 2;
1488 req->dst.x_offset = req_rga->dst.x_offset - req_rga->dst.act_w + 1;
1489 req->dst.y_offset = req_rga->dst.y_offset - req_rga->dst.act_h + 1;
1490 } else if (req_rga->sina == -65536 && req_rga->cosa == 0) {
1491 /* totate 270 */
1492 req->rotate_mode = 3;
1493 req->dst.y_offset = req_rga->dst.y_offset - req_rga->dst.act_w + 1;
1494 req->dst.act_w = req_rga->dst.act_h;
1495 req->dst.act_h = req_rga->dst.act_w;
1496 }
1497 break;
1498 case 2:
1499 //x_mirror
1500 req->rotate_mode |= (1 << 4);
1501 break;
1502 case 3:
1503 //y_mirror
1504 req->rotate_mode |= (2 << 4);
1505 break;
1506 case 4:
1507 //x_mirror+y_mirror
1508 req->rotate_mode |= (3 << 4);
1509 break;
1510 default:
1511 req->rotate_mode = 0;
1512 break;
1513 }
1514
1515 switch ((req_rga->rotate_mode & 0xF0) >> 4) {
1516 case 2:
1517 //x_mirror
1518 req->rotate_mode |= (1 << 4);
1519 break;
1520 case 3:
1521 //y_mirror
1522 req->rotate_mode |= (2 << 4);
1523 break;
1524 case 4:
1525 //x_mirror+y_mirror
1526 req->rotate_mode |= (3 << 4);
1527 break;
1528 }
1529
1530 if((req->dst.act_w > 2048) && (req->src.act_h < req->dst.act_h))
1531 req->scale_bicu_mode |= (1<<4);
1532 req->LUT_addr = req_rga->LUT_addr;
1533 req->rop_mask_addr = req_rga->rop_mask_addr;
1534 req->bitblt_mode = req_rga->bsfilter_flag;
1535 req->src_a_global_val = req_rga->alpha_global_value;
1536 req->dst_a_global_val = req_rga->alpha_global_value;
1537 req->rop_code = req_rga->rop_code;
1538 req->rop_mode = req_rga->alpha_rop_mode;
1539 req->color_fill_mode = req_rga->color_fill_mode;
1540 req->alpha_zero_key = req_rga->alpha_rop_mode >> 4;
1541 req->src_trans_mode = req_rga->src_trans_mode;
1542 req->color_key_min = req_rga->color_key_min;
1543 req->color_key_max = req_rga->color_key_max;
1544 req->fg_color = req_rga->fg_color;
1545 req->bg_color = req_rga->bg_color;
1546 memcpy(&req->gr_color, &req_rga->gr_color, sizeof(req_rga->gr_color));
1547 memcpy(&req->full_csc, &req_rga->full_csc, sizeof(req_rga->full_csc));
1548
1549 req->palette_mode = req_rga->palette_mode;
1550 req->yuv2rgb_mode = req_rga->yuv2rgb_mode;
1551 req->endian_mode = req_rga->endian_mode;
1552 req->rgb2yuv_mode = 0;
1553 req->fading_alpha_value = 0;
1554 req->fading_r_value = req_rga->fading.r;
1555 req->fading_g_value = req_rga->fading.g;
1556 req->fading_b_value = req_rga->fading.b;
1557
1558 /* alpha mode set */
1559 req->alpha_rop_flag = 0;
1560 req->alpha_rop_flag |= (((req_rga->alpha_rop_flag & 1))); // alpha_rop_enable
1561 req->alpha_rop_flag |= (((req_rga->alpha_rop_flag >> 1) & 1) << 1); // rop_enable
1562 req->alpha_rop_flag |= (((req_rga->alpha_rop_flag >> 2) & 1) << 2); // fading_enable
1563 req->alpha_rop_flag |= (((req_rga->alpha_rop_flag >> 4) & 1) << 3); // alpha_cal_mode_sel
1564 req->alpha_rop_flag |= (((req_rga->alpha_rop_flag >> 5) & 1) << 6); // dst_dither_down
1565 req->alpha_rop_flag |= (((req_rga->alpha_rop_flag >> 6) & 1) << 7); // gradient fill mode sel
1566
1567 req->alpha_rop_flag |= (((req_rga->alpha_rop_flag >> 8) & 1) << 8); // nn_quantize
1568 req->dither_mode = req_rga->dither_mode;
1569
1570 if (((req_rga->alpha_rop_flag) & 1)) {
1571 if ((req_rga->alpha_rop_flag >> 3) & 1) {
1572 /* porter duff alpha enable */
1573 switch (req_rga->PD_mode)
1574 {
1575 case 0: //dst = 0
1576 break;
1577 case 1: //dst = src
1578 req->alpha_mode_0 = 0x0212;
1579 req->alpha_mode_1 = 0x0212;
1580 break;
1581 case 2: //dst = dst
1582 req->alpha_mode_0 = 0x1202;
1583 req->alpha_mode_1 = 0x1202;
1584 break;
1585 case 3: //dst = (256*sc + (256 - sa)*dc) >> 8
1586 if((req_rga->alpha_rop_mode & 3) == 0) {
1587 /* both use globalAlpha. */
1588 alpha_mode_0 = 0x3010;
1589 alpha_mode_1 = 0x3010;
1590 }
1591 else if ((req_rga->alpha_rop_mode & 3) == 1) {
1592 /* dst use globalAlpha, and dst does not have pixelAlpha. */
1593 alpha_mode_0 = 0x3012;
1594 alpha_mode_1 = 0x3012;
1595 }
1596 else if ((req_rga->alpha_rop_mode & 3) == 2) {
1597 /* dst use globalAlpha, and dst has pixelAlpha. */
1598 alpha_mode_0 = 0x3014;
1599 alpha_mode_1 = 0x3014;
1600 }
1601 else {
1602 /* Do not use globalAlpha. */
1603 alpha_mode_0 = 0x3212;
1604 alpha_mode_1 = 0x3212;
1605 }
1606 req->alpha_mode_0 = alpha_mode_0;
1607 req->alpha_mode_1 = alpha_mode_1;
1608 break;
1609 case 4: //dst = (sc*(256-da) + 256*dc) >> 8
1610 /* Do not use globalAlpha. */
1611 req->alpha_mode_0 = 0x1232;
1612 req->alpha_mode_1 = 0x1232;
1613 break;
1614 case 5: //dst = (da*sc) >> 8
1615 break;
1616 case 6: //dst = (sa*dc) >> 8
1617 break;
1618 case 7: //dst = ((256-da)*sc) >> 8
1619 break;
1620 case 8: //dst = ((256-sa)*dc) >> 8
1621 break;
1622 case 9: //dst = (da*sc + (256-sa)*dc) >> 8
1623 req->alpha_mode_0 = 0x3040;
1624 req->alpha_mode_1 = 0x3040;
1625 break;
1626 case 10://dst = ((256-da)*sc + (sa*dc)) >> 8
1627 break;
1628 case 11://dst = ((256-da)*sc + (256-sa)*dc) >> 8;
1629 break;
1630 case 12:
1631 req->alpha_mode_0 = 0x0010;
1632 req->alpha_mode_1 = 0x0820;
1633 break;
1634 default:
1635 break;
1636 }
1637 /* Real color mode */
1638 if ((req_rga->alpha_rop_flag >> 9) & 1) {
1639 if (req->alpha_mode_0 & (0x01 << 1))
1640 req->alpha_mode_0 |= (1 << 7);
1641 if (req->alpha_mode_0 & (0x01 << 9))
1642 req->alpha_mode_0 |= (1 << 15);
1643 }
1644 }
1645 else {
1646 if((req_rga->alpha_rop_mode & 3) == 0) {
1647 req->alpha_mode_0 = 0x3040;
1648 req->alpha_mode_1 = 0x3040;
1649 }
1650 else if ((req_rga->alpha_rop_mode & 3) == 1) {
1651 req->alpha_mode_0 = 0x3042;
1652 req->alpha_mode_1 = 0x3242;
1653 }
1654 else if ((req_rga->alpha_rop_mode & 3) == 2) {
1655 req->alpha_mode_0 = 0x3044;
1656 req->alpha_mode_1 = 0x3044;
1657 }
1658 }
1659 }
1660
1661 if (req_rga->mmu_info.mmu_en && (req_rga->mmu_info.mmu_flag & 1) == 1) {
1662 req->mmu_info.src0_mmu_flag = 1;
1663 req->mmu_info.dst_mmu_flag = 1;
1664 if (req_rga->mmu_info.mmu_flag >> 31) {
1665 req->mmu_info.src0_mmu_flag = ((req_rga->mmu_info.mmu_flag >> 8) & 1);
1666 req->mmu_info.src1_mmu_flag = ((req_rga->mmu_info.mmu_flag >> 9) & 1);
1667 req->mmu_info.dst_mmu_flag = ((req_rga->mmu_info.mmu_flag >> 10) & 1);
1668 req->mmu_info.els_mmu_flag = ((req_rga->mmu_info.mmu_flag >> 11) & 1);
1669 }
1670 else {
1671 if (req_rga->src.yrgb_addr >= 0xa0000000) {
1672 req->mmu_info.src0_mmu_flag = 0;
1673 req->src.yrgb_addr = req_rga->src.yrgb_addr - 0x60000000;
1674 req->src.uv_addr = req_rga->src.uv_addr - 0x60000000;
1675 req->src.v_addr = req_rga->src.v_addr - 0x60000000;
1676 }
1677
1678 if (req_rga->dst.yrgb_addr >= 0xa0000000) {
1679 req->mmu_info.dst_mmu_flag = 0;
1680 req->dst.yrgb_addr = req_rga->dst.yrgb_addr - 0x60000000;
1681 }
1682
1683 if (req_rga->pat.yrgb_addr >= 0xa0000000) {
1684 req->mmu_info.src1_mmu_flag = 0;
1685 req->src1.yrgb_addr = req_rga->pat.yrgb_addr - 0x60000000;
1686 }
1687 }
1688 }
1689 }
1690