| /OK3568_Linux_fs/u-boot/drivers/clk/rockchip/ |
| H A D | clk_rv1108.c | 117 static uint32_t rkclk_pll_get_rate(struct rv1108_cru *cru, in rkclk_pll_get_rate() function
150 pll_rate = rkclk_pll_get_rate(cru, CLK_GENERAL); in rv1108_mac_set_clk()
152 pll_rate = rkclk_pll_get_rate(cru, CLK_ARM); in rv1108_mac_set_clk()
175 pll_rate = rkclk_pll_get_rate(cru, CLK_GENERAL); in rv1108_sfc_set_clk()
177 pll_rate = rkclk_pll_get_rate(cru, CLK_DDR); in rv1108_sfc_set_clk()
306 ulong parent_rate = rkclk_pll_get_rate(cru, CLK_GENERAL); in rv1108_aclk_bus_get_clk()
318 ulong parent_rate = rkclk_pll_get_rate(cru, CLK_GENERAL); in rv1108_aclk_bus_set_clk()
334 ulong parent_rate = rkclk_pll_get_rate(cru, CLK_GENERAL); in rv1108_aclk_peri_get_clk()
346 ulong parent_rate = rkclk_pll_get_rate(cru, CLK_GENERAL); in rv1108_hclk_peri_get_clk()
358 ulong parent_rate = rkclk_pll_get_rate(cru, CLK_GENERAL); in rv1108_pclk_peri_get_clk()
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| H A D | clk_rk3368.c | 223 static uint32_t rkclk_pll_get_rate(struct rk3368_cru *cru, in rkclk_pll_get_rate() function
315 pll_rate = rkclk_pll_get_rate(cru, GPLL); in rk3368_mmc_get_clk()
321 pll_rate = rkclk_pll_get_rate(cru, CPLL); in rk3368_mmc_get_clk()
596 parent = rkclk_pll_get_rate(cru, GPLL); in rk3368_bus_get_clk()
630 src_clk_div = DIV_ROUND_UP(rkclk_pll_get_rate(cru, GPLL), hz); in rk3368_bus_set_clk()
670 parent = rkclk_pll_get_rate(cru, GPLL); in rk3368_peri_get_clk()
704 src_clk_div = DIV_ROUND_UP(rkclk_pll_get_rate(cru, GPLL), hz); in rk3368_peri_set_clk()
746 parent = rkclk_pll_get_rate(cru, NPLL); in rk3368_vop_get_clk()
755 parent = rkclk_pll_get_rate(cru, CPLL); in rk3368_vop_get_clk()
757 parent = rkclk_pll_get_rate(cru, GPLL); in rk3368_vop_get_clk()
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| H A D | clk_rk3288.c | 269 static u32 rkclk_pll_get_rate(struct rk3288_cru *cru, in rkclk_pll_get_rate() function
482 gpll_rate = rkclk_pll_get_rate(cru, CLK_GENERAL); in rockchip_vop_set_clk()
483 npll_rate = rkclk_pll_get_rate(cru, CLK_NEW); in rockchip_vop_set_clk()
873 parent_rate = rkclk_pll_get_rate(cru, CLK_GENERAL); in rockchip_aclk_peri_get_clk()
875 parent_rate = rkclk_pll_get_rate(cru, CLK_CODEC); in rockchip_aclk_peri_get_clk()
891 parent_rate = rkclk_pll_get_rate(cru, CLK_GENERAL); in rockchip_aclk_cpu_get_clk()
893 parent_rate = rkclk_pll_get_rate(cru, CLK_CODEC); in rockchip_aclk_cpu_get_clk()
1083 gclk_rate = rkclk_pll_get_rate(priv->cru, CLK_GENERAL); in rk3288_clk_get_rate()
1086 new_rate = rkclk_pll_get_rate(priv->cru, clk->id); in rk3288_clk_get_rate()
1157 gclk_rate = rkclk_pll_get_rate(priv->cru, CLK_GENERAL); in rk3288_clk_set_rate()
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| H A D | clk_rk3036.c | 201 static uint32_t rkclk_pll_get_rate(struct rk3036_cru *cru, in rkclk_pll_get_rate() function
462 ulong gclk_rate = rkclk_pll_get_rate(priv->cru, CLK_GENERAL); in rk3036_clk_get_rate()
466 return rkclk_pll_get_rate(priv->cru, clk->id); in rk3036_clk_get_rate()
485 gclk_rate = rkclk_pll_get_rate(priv->cru, CLK_GENERAL); in rk3036_clk_set_rate()
537 priv->armclk_enter_hz = rkclk_pll_get_rate(priv->cru, in rk3036_clk_probe()
541 priv->armclk_init_hz = rkclk_pll_get_rate(priv->cru, in rk3036_clk_probe()
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| H A D | clk_rk3066.c | 247 static uint32_t rkclk_pll_get_rate(struct rk3066_cru *cru, in rkclk_pll_get_rate() function
477 gclk_rate = rkclk_pll_get_rate(priv->cru, CLK_GENERAL); in rk3066_clk_get_rate()
480 new_rate = rkclk_pll_get_rate(priv->cru, clk->id); in rk3066_clk_get_rate()
571 priv->armclk_enter_hz = rkclk_pll_get_rate(priv->cru, in rk3066_clk_probe()
575 priv->armclk_init_hz = rkclk_pll_get_rate(priv->cru, in rk3066_clk_probe()
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| H A D | clk_rk3188.c | 245 static uint32_t rkclk_pll_get_rate(struct rk3188_cru *cru, in rkclk_pll_get_rate() function
507 gclk_rate = rkclk_pll_get_rate(priv->cru, CLK_GENERAL); in rk3188_clk_get_rate()
510 new_rate = rkclk_pll_get_rate(priv->cru, clk->id); in rk3188_clk_get_rate()
614 priv->armclk_enter_hz = rkclk_pll_get_rate(priv->cru, in rk3188_clk_probe()
618 priv->armclk_init_hz = rkclk_pll_get_rate(priv->cru, in rk3188_clk_probe()
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| H A D | clk_rk3399.c | 342 static uint32_t rkclk_pll_get_rate(u32 *pll_con) in rkclk_pll_get_rate() function
442 return rkclk_pll_get_rate(pll_con); in rk3399_pll_get_rate()
1412 if (rkclk_pll_get_rate(&cru->npll_con[0]) != NPLL_HZ) in rkclk_init()
1415 if (rkclk_pll_get_rate(&cru->gpll_con[0]) == GPLL_HZ) in rkclk_init()
1519 rkclk_pll_get_rate(&priv->cru->apll_l_con[0]); in rk3399_clk_probe()
1522 rkclk_pll_get_rate(&priv->cru->apll_b_con[0]); in rk3399_clk_probe()
1526 rkclk_pll_get_rate(&priv->cru->apll_l_con[0]); in rk3399_clk_probe()
1529 rkclk_pll_get_rate(&priv->cru->apll_b_con[0]); in rk3399_clk_probe()
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| H A D | clk_px30.c | 269 static uint32_t rkclk_pll_get_rate(struct px30_pll *pll, unsigned int *mode, in rkclk_pll_get_rate() function
823 parent = rkclk_pll_get_rate(&cru->pll[CPLL], &cru->mode, CPLL); in px30_vop_get_clk()
828 parent = rkclk_pll_get_rate(&cru->pll[NPLL], &cru->mode, NPLL); in px30_vop_get_clk()
1234 return rkclk_pll_get_rate(&cru->pll[pll_id], &cru->mode, pll_id); in px30_clk_get_pll_rate()
1244 return rkclk_pll_get_rate(&cru->pll[pll_id], &cru->mode, pll_id); in px30_clk_set_pll_rate()
1766 return rkclk_pll_get_rate(&pmucru->pll, &pmucru->pmu_mode, GPLL); in px30_gpll_get_pmuclk()
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