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Searched refs:ref_and_mask (Results 1 – 12 of 12) sorted by relevance

/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/amdgpu/
H A Dsdma_v2_4.c280 u32 ref_and_mask = 0; in sdma_v2_4_ring_emit_hdp_flush() local
283 ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA0, 1); in sdma_v2_4_ring_emit_hdp_flush()
285 ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA1, 1); in sdma_v2_4_ring_emit_hdp_flush()
292 amdgpu_ring_write(ring, ref_and_mask); /* reference */ in sdma_v2_4_ring_emit_hdp_flush()
293 amdgpu_ring_write(ring, ref_and_mask); /* mask */ in sdma_v2_4_ring_emit_hdp_flush()
H A Dsdma_v3_0.c454 u32 ref_and_mask = 0; in sdma_v3_0_ring_emit_hdp_flush() local
457 ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA0, 1); in sdma_v3_0_ring_emit_hdp_flush()
459 ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA1, 1); in sdma_v3_0_ring_emit_hdp_flush()
466 amdgpu_ring_write(ring, ref_and_mask); /* reference */ in sdma_v3_0_ring_emit_hdp_flush()
467 amdgpu_ring_write(ring, ref_and_mask); /* mask */ in sdma_v3_0_ring_emit_hdp_flush()
H A Dcik_sdma.c251 u32 ref_and_mask; in cik_sdma_ring_emit_hdp_flush() local
254 ref_and_mask = GPU_HDP_FLUSH_DONE__SDMA0_MASK; in cik_sdma_ring_emit_hdp_flush()
256 ref_and_mask = GPU_HDP_FLUSH_DONE__SDMA1_MASK; in cik_sdma_ring_emit_hdp_flush()
261 amdgpu_ring_write(ring, ref_and_mask); /* reference */ in cik_sdma_ring_emit_hdp_flush()
262 amdgpu_ring_write(ring, ref_and_mask); /* mask */ in cik_sdma_ring_emit_hdp_flush()
H A Dsdma_v5_0.c453 u32 ref_and_mask = 0; in sdma_v5_0_ring_emit_hdp_flush() local
457 ref_and_mask = nbio_hf_reg->ref_and_mask_sdma0; in sdma_v5_0_ring_emit_hdp_flush()
459 ref_and_mask = nbio_hf_reg->ref_and_mask_sdma1; in sdma_v5_0_ring_emit_hdp_flush()
466 amdgpu_ring_write(ring, ref_and_mask); /* reference */ in sdma_v5_0_ring_emit_hdp_flush()
467 amdgpu_ring_write(ring, ref_and_mask); /* mask */ in sdma_v5_0_ring_emit_hdp_flush()
H A Dsdma_v5_2.c390 u32 ref_and_mask = 0; in sdma_v5_2_ring_emit_hdp_flush() local
393 ref_and_mask = nbio_hf_reg->ref_and_mask_sdma0 << ring->me; in sdma_v5_2_ring_emit_hdp_flush()
400 amdgpu_ring_write(ring, ref_and_mask); /* reference */ in sdma_v5_2_ring_emit_hdp_flush()
401 amdgpu_ring_write(ring, ref_and_mask); /* mask */ in sdma_v5_2_ring_emit_hdp_flush()
H A Dsdma_v4_0.c900 u32 ref_and_mask = 0; in sdma_v4_0_ring_emit_hdp_flush() local
903 ref_and_mask = nbio_hf_reg->ref_and_mask_sdma0 << ring->me; in sdma_v4_0_ring_emit_hdp_flush()
908 ref_and_mask, ref_and_mask, 10); in sdma_v4_0_ring_emit_hdp_flush()
H A Dgfx_v7_0.c2131 u32 ref_and_mask; in gfx_v7_0_ring_emit_hdp_flush() local
2137 ref_and_mask = GPU_HDP_FLUSH_DONE__CP2_MASK << ring->pipe; in gfx_v7_0_ring_emit_hdp_flush()
2140 ref_and_mask = GPU_HDP_FLUSH_DONE__CP6_MASK << ring->pipe; in gfx_v7_0_ring_emit_hdp_flush()
2146 ref_and_mask = GPU_HDP_FLUSH_DONE__CP0_MASK; in gfx_v7_0_ring_emit_hdp_flush()
2155 amdgpu_ring_write(ring, ref_and_mask); in gfx_v7_0_ring_emit_hdp_flush()
2156 amdgpu_ring_write(ring, ref_and_mask); in gfx_v7_0_ring_emit_hdp_flush()
H A Dgfx_v8_0.c6071 u32 ref_and_mask, reg_mem_engine; in gfx_v8_0_ring_emit_hdp_flush() local
6077 ref_and_mask = GPU_HDP_FLUSH_DONE__CP2_MASK << ring->pipe; in gfx_v8_0_ring_emit_hdp_flush()
6080 ref_and_mask = GPU_HDP_FLUSH_DONE__CP6_MASK << ring->pipe; in gfx_v8_0_ring_emit_hdp_flush()
6087 ref_and_mask = GPU_HDP_FLUSH_DONE__CP0_MASK; in gfx_v8_0_ring_emit_hdp_flush()
6097 amdgpu_ring_write(ring, ref_and_mask); in gfx_v8_0_ring_emit_hdp_flush()
6098 amdgpu_ring_write(ring, ref_and_mask); in gfx_v8_0_ring_emit_hdp_flush()
H A Dgfx_v9_0.c5244 u32 ref_and_mask, reg_mem_engine; in gfx_v9_0_ring_emit_hdp_flush() local
5250 ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe; in gfx_v9_0_ring_emit_hdp_flush()
5253 ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe; in gfx_v9_0_ring_emit_hdp_flush()
5260 ref_and_mask = nbio_hf_reg->ref_and_mask_cp0; in gfx_v9_0_ring_emit_hdp_flush()
5267 ref_and_mask, ref_and_mask, 0x20); in gfx_v9_0_ring_emit_hdp_flush()
H A Dgfx_v10_0.c7761 u32 ref_and_mask, reg_mem_engine; in gfx_v10_0_ring_emit_hdp_flush() local
7767 ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe; in gfx_v10_0_ring_emit_hdp_flush()
7770 ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe; in gfx_v10_0_ring_emit_hdp_flush()
7777 ref_and_mask = nbio_hf_reg->ref_and_mask_cp0; in gfx_v10_0_ring_emit_hdp_flush()
7784 ref_and_mask, ref_and_mask, 0x20); in gfx_v10_0_ring_emit_hdp_flush()
/OK3568_Linux_fs/kernel/drivers/gpu/drm/radeon/
H A Dcik_sdma.c175 u32 ref_and_mask; in cik_sdma_hdp_flush_ring_emit() local
178 ref_and_mask = SDMA0; in cik_sdma_hdp_flush_ring_emit()
180 ref_and_mask = SDMA1; in cik_sdma_hdp_flush_ring_emit()
185 radeon_ring_write(ring, ref_and_mask); /* reference */ in cik_sdma_hdp_flush_ring_emit()
186 radeon_ring_write(ring, ref_and_mask); /* mask */ in cik_sdma_hdp_flush_ring_emit()
H A Dcik.c3508 u32 ref_and_mask; in cik_hdp_flush_cp_ring_emit() local
3516 ref_and_mask = CP2 << ring->pipe; in cik_hdp_flush_cp_ring_emit()
3519 ref_and_mask = CP6 << ring->pipe; in cik_hdp_flush_cp_ring_emit()
3526 ref_and_mask = CP0; in cik_hdp_flush_cp_ring_emit()
3536 radeon_ring_write(ring, ref_and_mask); in cik_hdp_flush_cp_ring_emit()
3537 radeon_ring_write(ring, ref_and_mask); in cik_hdp_flush_cp_ring_emit()