Searched refs:pllp (Results 1 – 3 of 3) sorted by relevance
204 u16 pllm, plln, pllp; in clock_get() local208 pllp = ((((readl(&STM32_RCC->pllcfgr) & RCC_PLLCFGR_PLLP_MASK) in clock_get()210 sysclk = ((CONFIG_STM32_HSE_HZ / pllm) * plln) / pllp; in clock_get()
190 u16 pllm, plln, pllp; in stm32_clk_get_rate() local194 pllp = ((((readl(®s->pllcfgr) & RCC_PLLCFGR_PLLP_MASK) in stm32_clk_get_rate()196 sysclk = ((CONFIG_STM32_HSE_HZ / pllm) * plln) / pllp; in stm32_clk_get_rate()
1244 static void tegra210_pllp_set_defaults(struct tegra_clk_pll *pllp) in tegra210_pllp_set_defaults() argument1247 u32 val = readl_relaxed(clk_base + pllp->params->base_reg); in tegra210_pllp_set_defaults()1249 pllp->params->defaults_set = true; in tegra210_pllp_set_defaults()1257 pllp_check_defaults(pllp, true); in tegra210_pllp_set_defaults()1258 if (!pllp->params->defaults_set) in tegra210_pllp_set_defaults()1262 val = readl_relaxed(clk_base + pllp->params->ext_misc_reg[0]); in tegra210_pllp_set_defaults()1266 writel_relaxed(val, clk_base + pllp->params->ext_misc_reg[0]); in tegra210_pllp_set_defaults()1274 clk_base + pllp->params->ext_misc_reg[0]); in tegra210_pllp_set_defaults()1277 val = readl_relaxed(clk_base + pllp->params->ext_misc_reg[1]); in tegra210_pllp_set_defaults()1281 writel_relaxed(val, clk_base + pllp->params->ext_misc_reg[1]); in tegra210_pllp_set_defaults()