Searched refs:hclkdiv_ctrl (Results 1 – 2 of 2) sorted by relevance
74 val = readl(&clk->hclkdiv_ctrl) & CLK_HCLK_ARM_PLL_DIV_MASK; in get_hclk_clk_div()88 val = readl(&clk->hclkdiv_ctrl) & CLK_HCLK_PERIPH_DIV_MASK; in get_periph_clk_div()112 switch (readl(&clk->hclkdiv_ctrl) & CLK_HCLK_DDRAM_MASK) { in get_sdram_clk_rate()122 switch (readl(&clk->hclkdiv_ctrl) & CLK_HCLK_ARM_PLL_DIV_MASK) { in get_sdram_clk_rate()
32 u32 hclkdiv_ctrl; /* HCLK Divider Control Register */ member