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Searched refs:dv_ddr2_regs_ctrl (Results 1 – 3 of 3) sorted by relevance

/OK3568_Linux_fs/u-boot/arch/arm/mach-davinci/
H A Dda850_lowlevel.c188 writel(CONFIG_SYS_DA850_DDR2_DDRPHYCR, &dv_ddr2_regs_ctrl->ddrphycr); in da850_ddr_setup()
207 setbits_le32(&dv_ddr2_regs_ctrl->sdbcr, DV_DDR_BOOTUNLOCK); in da850_ddr_setup()
217 writel(tmp, &dv_ddr2_regs_ctrl->sdbcr); in da850_ddr_setup()
223 &dv_ddr2_regs_ctrl->sdbcr2); in da850_ddr_setup()
225 writel(CONFIG_SYS_DA850_DDR2_SDTIMR, &dv_ddr2_regs_ctrl->sdtimr); in da850_ddr_setup()
226 writel(CONFIG_SYS_DA850_DDR2_SDTIMR2, &dv_ddr2_regs_ctrl->sdtimr2); in da850_ddr_setup()
230 writel(tmp, &dv_ddr2_regs_ctrl->sdbcr); in da850_ddr_setup()
239 &dv_ddr2_regs_ctrl->sdrcr); in da850_ddr_setup()
247 clrbits_le32(&dv_ddr2_regs_ctrl->sdrcr, in da850_ddr_setup()
249 writel(CONFIG_SYS_DA850_DDR2_PBBPR, &dv_ddr2_regs_ctrl->pbbpr); in da850_ddr_setup()
H A Ddm365_lowlevel.c217 writel(CONFIG_SYS_DM36x_DDR2_DDRPHYCR, &dv_ddr2_regs_ctrl->ddrphycr); in dm365_ddr_setup()
221 &dv_ddr2_regs_ctrl->sdbcr); in dm365_ddr_setup()
223 &dv_ddr2_regs_ctrl->sdbcr); in dm365_ddr_setup()
226 writel(CONFIG_SYS_DM36x_DDR2_SDTIMR, &dv_ddr2_regs_ctrl->sdtimr); in dm365_ddr_setup()
228 writel(CONFIG_SYS_DM36x_DDR2_SDTIMR2, &dv_ddr2_regs_ctrl->sdtimr2); in dm365_ddr_setup()
230 writel(CONFIG_SYS_DM36x_DDR2_PBBPR, &dv_ddr2_regs_ctrl->pbbpr); in dm365_ddr_setup()
232 writel(CONFIG_SYS_DM36x_DDR2_SDBCR, &dv_ddr2_regs_ctrl->sdbcr); in dm365_ddr_setup()
235 writel(CONFIG_SYS_DM36x_DDR2_SDRCR, &dv_ddr2_regs_ctrl->sdrcr); in dm365_ddr_setup()
/OK3568_Linux_fs/u-boot/arch/arm/mach-davinci/include/mach/
H A Dddr2_defs.h14 struct dv_ddr2_regs_ctrl { struct
81 #define dv_ddr2_regs_ctrl \ macro
82 ((struct dv_ddr2_regs_ctrl *)DAVINCI_DDR_EMIF_CTRL_BASE)