1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright (C) 2011 3*4882a593Smuzhiyun * Heiko Schocher, DENX Software Engineering, hs@denx.de. 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun #ifndef _DV_DDR2_DEFS_H_ 8*4882a593Smuzhiyun #define _DV_DDR2_DEFS_H_ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun /* 11*4882a593Smuzhiyun * DDR2 Memory Ctrl Register structure 12*4882a593Smuzhiyun * See sprueh7d.pdf for more details. 13*4882a593Smuzhiyun */ 14*4882a593Smuzhiyun struct dv_ddr2_regs_ctrl { 15*4882a593Smuzhiyun unsigned char rsvd0[4]; /* 0x00 */ 16*4882a593Smuzhiyun unsigned int sdrstat; /* 0x04 */ 17*4882a593Smuzhiyun unsigned int sdbcr; /* 0x08 */ 18*4882a593Smuzhiyun unsigned int sdrcr; /* 0x0C */ 19*4882a593Smuzhiyun unsigned int sdtimr; /* 0x10 */ 20*4882a593Smuzhiyun unsigned int sdtimr2; /* 0x14 */ 21*4882a593Smuzhiyun unsigned char rsvd1[4]; /* 0x18 */ 22*4882a593Smuzhiyun unsigned int sdbcr2; /* 0x1C */ 23*4882a593Smuzhiyun unsigned int pbbpr; /* 0x20 */ 24*4882a593Smuzhiyun unsigned char rsvd2[156]; /* 0x24 */ 25*4882a593Smuzhiyun unsigned int irr; /* 0xC0 */ 26*4882a593Smuzhiyun unsigned int imr; /* 0xC4 */ 27*4882a593Smuzhiyun unsigned int imsr; /* 0xC8 */ 28*4882a593Smuzhiyun unsigned int imcr; /* 0xCC */ 29*4882a593Smuzhiyun unsigned char rsvd3[20]; /* 0xD0 */ 30*4882a593Smuzhiyun unsigned int ddrphycr; /* 0xE4 */ 31*4882a593Smuzhiyun unsigned int ddrphycr2; /* 0xE8 */ 32*4882a593Smuzhiyun unsigned char rsvd4[4]; /* 0xEC */ 33*4882a593Smuzhiyun }; 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun #define DV_DDR_PHY_PWRDNEN 0x40 36*4882a593Smuzhiyun #define DV_DDR_PHY_EXT_STRBEN 0x80 37*4882a593Smuzhiyun #define DV_DDR_PHY_RD_LATENCY_SHIFT 0 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun #define DV_DDR_SDTMR1_RFC_SHIFT 25 40*4882a593Smuzhiyun #define DV_DDR_SDTMR1_RP_SHIFT 22 41*4882a593Smuzhiyun #define DV_DDR_SDTMR1_RCD_SHIFT 19 42*4882a593Smuzhiyun #define DV_DDR_SDTMR1_WR_SHIFT 16 43*4882a593Smuzhiyun #define DV_DDR_SDTMR1_RAS_SHIFT 11 44*4882a593Smuzhiyun #define DV_DDR_SDTMR1_RC_SHIFT 6 45*4882a593Smuzhiyun #define DV_DDR_SDTMR1_RRD_SHIFT 3 46*4882a593Smuzhiyun #define DV_DDR_SDTMR1_WTR_SHIFT 0 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun #define DV_DDR_SDTMR2_RASMAX_SHIFT 27 49*4882a593Smuzhiyun #define DV_DDR_SDTMR2_XP_SHIFT 25 50*4882a593Smuzhiyun #define DV_DDR_SDTMR2_ODT_SHIFT 23 51*4882a593Smuzhiyun #define DV_DDR_SDTMR2_XSNR_SHIFT 16 52*4882a593Smuzhiyun #define DV_DDR_SDTMR2_XSRD_SHIFT 8 53*4882a593Smuzhiyun #define DV_DDR_SDTMR2_RTP_SHIFT 5 54*4882a593Smuzhiyun #define DV_DDR_SDTMR2_CKE_SHIFT 0 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun #define DV_DDR_SDCR_DDR2TERM1_SHIFT 27 57*4882a593Smuzhiyun #define DV_DDR_SDCR_IBANK_POS_SHIFT 26 58*4882a593Smuzhiyun #define DV_DDR_SDCR_MSDRAMEN_SHIFT 25 59*4882a593Smuzhiyun #define DV_DDR_SDCR_DDRDRIVE1_SHIFT 24 60*4882a593Smuzhiyun #define DV_DDR_SDCR_BOOTUNLOCK_SHIFT 23 61*4882a593Smuzhiyun #define DV_DDR_SDCR_DDR_DDQS_SHIFT 22 62*4882a593Smuzhiyun #define DV_DDR_SDCR_DDR2EN_SHIFT 20 63*4882a593Smuzhiyun #define DV_DDR_SDCR_DDRDRIVE0_SHIFT 18 64*4882a593Smuzhiyun #define DV_DDR_SDCR_DDREN_SHIFT 17 65*4882a593Smuzhiyun #define DV_DDR_SDCR_SDRAMEN_SHIFT 16 66*4882a593Smuzhiyun #define DV_DDR_SDCR_TIMUNLOCK_SHIFT 15 67*4882a593Smuzhiyun #define DV_DDR_SDCR_BUS_WIDTH_SHIFT 14 68*4882a593Smuzhiyun #define DV_DDR_SDCR_CL_SHIFT 9 69*4882a593Smuzhiyun #define DV_DDR_SDCR_IBANK_SHIFT 4 70*4882a593Smuzhiyun #define DV_DDR_SDCR_PAGESIZE_SHIFT 0 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun #define DV_DDR_SDRCR_LPMODEN (1 << 31) 73*4882a593Smuzhiyun #define DV_DDR_SDRCR_MCLKSTOPEN (1 << 30) 74*4882a593Smuzhiyun 75*4882a593Smuzhiyun #define DV_DDR_SRCR_LPMODEN_SHIFT 31 76*4882a593Smuzhiyun #define DV_DDR_SRCR_MCLKSTOPEN_SHIFT 30 77*4882a593Smuzhiyun 78*4882a593Smuzhiyun #define DV_DDR_BOOTUNLOCK (1 << DV_DDR_SDCR_BOOTUNLOCK_SHIFT) 79*4882a593Smuzhiyun #define DV_DDR_TIMUNLOCK (1 << DV_DDR_SDCR_TIMUNLOCK_SHIFT) 80*4882a593Smuzhiyun 81*4882a593Smuzhiyun #define dv_ddr2_regs_ctrl \ 82*4882a593Smuzhiyun ((struct dv_ddr2_regs_ctrl *)DAVINCI_DDR_EMIF_CTRL_BASE) 83*4882a593Smuzhiyun 84*4882a593Smuzhiyun #endif /* _DV_DDR2_DEFS_H_ */ 85