| /OK3568_Linux_fs/kernel/drivers/clk/mmp/ |
| H A D | clk-mix.c | 134 static int _set_rate(struct mmp_clk_mix *mix, u32 mux_val, u32 div_val, in _set_rate() argument
159 mux_div |= MMP_CLK_BITS_SET_VAL(div_val, width, shift); in _set_rate()
280 u32 div_val, mux_val; in mmp_clk_mix_set_rate_and_parent() local
283 div_val = _get_div_val(mix, div); in mmp_clk_mix_set_rate_and_parent()
286 return _set_rate(mix, mux_val, div_val, 1, 1); in mmp_clk_mix_set_rate_and_parent()
353 u32 div_val, mux_val; in mmp_clk_set_parent() local
364 div_val = _get_div_val(mix, item->divisor); in mmp_clk_set_parent()
370 div_val = 0; in mmp_clk_set_parent()
373 return _set_rate(mix, mux_val, div_val, 1, div_val ? 1 : 0); in mmp_clk_set_parent()
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| /OK3568_Linux_fs/kernel/drivers/gpu/drm/rockchip/ |
| H A D | rockchip_vop2_clk.c | 226 div = 1 << vop2_clk->div_val; in vop2_clk_div_recalc_rate()
257 int div_val; in vop2_clk_div_set_rate() local
259 div_val = vop2_div_get_val(rate, parent_rate); in vop2_clk_div_set_rate()
260 vop2_clk->div_val = div_val; in vop2_clk_div_set_rate()
263 clk_hw_get_name(hw), parent_rate, rate, div_val); in vop2_clk_div_set_rate()
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| H A D | rockchip_drm_vop2.c | 908 int div_val; member
7394 VOP_MODULE_SET(vop2, dsc, dsc_txp_clk_div, dsc_txp_clk->div_val); in vop2_crtc_enable_dsc()
7395 VOP_MODULE_SET(vop2, dsc, dsc_pxl_clk_div, dsc_pxl_clk->div_val); in vop2_crtc_enable_dsc()
7396 VOP_MODULE_SET(vop2, dsc, dsc_cds_clk_div, dsc_cds_clk->div_val); in vop2_crtc_enable_dsc()
7465 dsc_htotal = htotal * (1 << dclk_core->div_val) / in vop2_crtc_enable_dsc()
7466 ((1 << dsc_txp_clk->div_val) * (1 << dsc_cds_clk->div_val)); in vop2_crtc_enable_dsc()
7502 vcstate->dsc_txp_clk_rate, dsc_txp_clk->div_val, in vop2_crtc_enable_dsc()
7503 vcstate->dsc_pxl_clk_rate, dsc_pxl_clk->div_val, in vop2_crtc_enable_dsc()
7504 vcstate->dsc_cds_clk_rate, dsc_cds_clk->div_val); in vop2_crtc_enable_dsc()
7867 VOP_CTRL_SET(vop2, mipi0_pixclk_div, if_pixclk->div_val); in vop2_crtc_atomic_enable()
[all …]
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| /OK3568_Linux_fs/kernel/drivers/clk/imx/ |
| H A D | clk-pll14xx.c | 184 u32 tmp, div_val; in clk_pll1416x_set_rate() local
217 div_val = (rate->mdiv << MDIV_SHIFT) | (rate->pdiv << PDIV_SHIFT) | in clk_pll1416x_set_rate()
219 writel_relaxed(div_val, pll->base + 0x4); in clk_pll1416x_set_rate()
250 u32 tmp, div_val; in clk_pll1443x_set_rate() local
282 div_val = (rate->mdiv << MDIV_SHIFT) | (rate->pdiv << PDIV_SHIFT) | in clk_pll1443x_set_rate()
284 writel_relaxed(div_val, pll->base + 0x4); in clk_pll1443x_set_rate()
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| /OK3568_Linux_fs/kernel/drivers/clk/x86/ |
| H A D | clk-cgu.h | 192 unsigned int div_val; member
240 .div_val = _v, \
278 .div_val = _v, \
298 .div_val = _v, \
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| H A D | clk-cgu.c | 32 list->div_width, list->div_val); in lgm_clk_register_fixed()
256 lgm_set_clk_val(div->membase, reg, shift, width, list->div_val); in lgm_clk_register_divider()
279 list->div_width, list->div_val); in lgm_clk_register_fixed_factor()
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| /OK3568_Linux_fs/kernel/drivers/media/cec/platform/s5p/ |
| H A D | exynos_hdmi_cecctrl.c | 25 u32 div_ratio, div_val; in s5p_cec_set_divider() local
42 div_val = CEC_DIV_RATIO * 0.00005 - 1; in s5p_cec_set_divider()
47 writeb(div_val, cec->reg + S5P_CEC_DIVISOR_0); in s5p_cec_set_divider()
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| /OK3568_Linux_fs/kernel/drivers/pwm/ |
| H A D | pwm-rockchip-i2s.c | 137 unsigned int div_val; in rockchip_i2s_pwm_config() local
167 div_val = readl_relaxed(pc->base + pc->data->reg_clkdiv); in rockchip_i2s_pwm_config()
168 div_val &= ~pc->data->mask_clkdiv; in rockchip_i2s_pwm_config()
170 | div_val, pc->base + pc->data->reg_clkdiv); in rockchip_i2s_pwm_config()
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