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Searched refs:div_bits (Results 1 – 8 of 8) sorted by relevance

/OK3568_Linux_fs/kernel/drivers/clk/ingenic/
H A Dx1000-cgu.c102 u32 usbpcr1, div_bits; in x1000_otg_phy_set_rate() local
106 div_bits = USBPCR1_REFCLKDIV_12; in x1000_otg_phy_set_rate()
110 div_bits = USBPCR1_REFCLKDIV_24; in x1000_otg_phy_set_rate()
114 div_bits = USBPCR1_REFCLKDIV_48; in x1000_otg_phy_set_rate()
125 usbpcr1 |= div_bits; in x1000_otg_phy_set_rate()
H A Djz4780-cgu.c150 u32 usbpcr1, div_bits; in jz4780_otg_phy_set_rate() local
154 div_bits = USBPCR1_REFCLKDIV_12; in jz4780_otg_phy_set_rate()
158 div_bits = USBPCR1_REFCLKDIV_19_2; in jz4780_otg_phy_set_rate()
162 div_bits = USBPCR1_REFCLKDIV_24; in jz4780_otg_phy_set_rate()
166 div_bits = USBPCR1_REFCLKDIV_48; in jz4780_otg_phy_set_rate()
177 usbpcr1 |= div_bits; in jz4780_otg_phy_set_rate()
/OK3568_Linux_fs/kernel/drivers/clk/hisilicon/
H A Dclk-hi3620.c228 u32 div_bits; member
244 u32 div_bits; member
373 val = mmc_clk_delay(val, div, mclk->div_off, mclk->div_bits); in mmc_clk_set_timing()
434 mclk->div_bits = mmc_clk->div_bits; in hisi_register_clk_mmc()
/OK3568_Linux_fs/buildroot/dl/sox/git/src/
H A Dau.c192 bits_per_sample, div_bits(data_size, bits_per_sample), sox_true); in startread()
H A Draw.c64 div_bits(lsx_filelength(ft), ft->encoding.bits_per_sample); in lsx_rawstart()
H A Dsox_i.h232 #define div_bits(size, bits) ((uint64_t)(size) * 8 / bits) macro
H A Dformats_i.c80 …uint64_t calculated_length = div_bits(lsx_filelength(ft) - ft->data_start, ft->encoding.bits_per_s… in lsx_check_read_params()
H A Dwav.c967 wav->numSamples = div_bits(qwDataLength, ft->encoding.bits_per_sample) in startread()