Searched refs:div4 (Results 1 – 7 of 7) sorted by relevance
33 unsigned int div4; member69 unsigned int div4; member
43 - clock-names: shall be "pll0_sysclk3", "div4.5"71 div4p5_clk: div4.5 {81 clock-names = "pll0_sysclk3", "div4.5";
39 u32 div4; /* 60 */ member
126 "cga-pll1-div4";141 clock-names = "pll1cga", "pll1cga-div2", "pll1cga-div4";
133 offset = pllctl_reg(data->pll, div4) + (i - 3); in configure_main_pll()
400 div4p5_clk: div4.5 {410 clock-names = "pll0_sysclk3", "div4.5";
551 #define div4(v) ((v)>>2) macro