1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * keystone2: common pll clock definitions 3*4882a593Smuzhiyun * (C) Copyright 2012-2014 4*4882a593Smuzhiyun * Texas Instruments Incorporated, <www.ti.com> 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #ifndef _CLOCK_DEFS_H_ 10*4882a593Smuzhiyun #define _CLOCK_DEFS_H_ 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #include <asm/arch/hardware.h> 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun /* PLL Control Registers */ 15*4882a593Smuzhiyun struct pllctl_regs { 16*4882a593Smuzhiyun u32 ctl; /* 00 */ 17*4882a593Smuzhiyun u32 ocsel; /* 04 */ 18*4882a593Smuzhiyun u32 secctl; /* 08 */ 19*4882a593Smuzhiyun u32 resv0; 20*4882a593Smuzhiyun u32 mult; /* 10 */ 21*4882a593Smuzhiyun u32 prediv; /* 14 */ 22*4882a593Smuzhiyun u32 div1; /* 18 */ 23*4882a593Smuzhiyun u32 div2; /* 1c */ 24*4882a593Smuzhiyun u32 div3; /* 20 */ 25*4882a593Smuzhiyun u32 oscdiv1; /* 24 */ 26*4882a593Smuzhiyun u32 resv1; /* 28 */ 27*4882a593Smuzhiyun u32 bpdiv; /* 2c */ 28*4882a593Smuzhiyun u32 wakeup; /* 30 */ 29*4882a593Smuzhiyun u32 resv2; 30*4882a593Smuzhiyun u32 cmd; /* 38 */ 31*4882a593Smuzhiyun u32 stat; /* 3c */ 32*4882a593Smuzhiyun u32 alnctl; /* 40 */ 33*4882a593Smuzhiyun u32 dchange; /* 44 */ 34*4882a593Smuzhiyun u32 cken; /* 48 */ 35*4882a593Smuzhiyun u32 ckstat; /* 4c */ 36*4882a593Smuzhiyun u32 systat; /* 50 */ 37*4882a593Smuzhiyun u32 ckctl; /* 54 */ 38*4882a593Smuzhiyun u32 resv3[2]; 39*4882a593Smuzhiyun u32 div4; /* 60 */ 40*4882a593Smuzhiyun u32 div5; /* 64 */ 41*4882a593Smuzhiyun u32 div6; /* 68 */ 42*4882a593Smuzhiyun u32 div7; /* 6c */ 43*4882a593Smuzhiyun u32 div8; /* 70 */ 44*4882a593Smuzhiyun u32 div9; /* 74 */ 45*4882a593Smuzhiyun u32 div10; /* 78 */ 46*4882a593Smuzhiyun u32 div11; /* 7c */ 47*4882a593Smuzhiyun u32 div12; /* 80 */ 48*4882a593Smuzhiyun }; 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun static struct pllctl_regs *pllctl_regs[] = { 51*4882a593Smuzhiyun (struct pllctl_regs *)(KS2_CLOCK_BASE + 0x100) 52*4882a593Smuzhiyun }; 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun #define pllctl_reg(pll, reg) (&(pllctl_regs[pll]->reg)) 55*4882a593Smuzhiyun #define pllctl_reg_read(pll, reg) __raw_readl(pllctl_reg(pll, reg)) 56*4882a593Smuzhiyun #define pllctl_reg_write(pll, reg, val) __raw_writel(val, pllctl_reg(pll, reg)) 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun #define pllctl_reg_rmw(pll, reg, mask, val) \ 59*4882a593Smuzhiyun pllctl_reg_write(pll, reg, \ 60*4882a593Smuzhiyun (pllctl_reg_read(pll, reg) & ~(mask)) | val) 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun #define pllctl_reg_setbits(pll, reg, mask) \ 63*4882a593Smuzhiyun pllctl_reg_rmw(pll, reg, 0, mask) 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun #define pllctl_reg_clrbits(pll, reg, mask) \ 66*4882a593Smuzhiyun pllctl_reg_rmw(pll, reg, mask, 0) 67*4882a593Smuzhiyun 68*4882a593Smuzhiyun #define pll0div_read(N) ((pllctl_reg_read(CORE_PLL, div##N) & 0xff) + 1) 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun /* PLLCTL Bits */ 71*4882a593Smuzhiyun #define PLLCTL_PLLENSRC_SHIF 5 72*4882a593Smuzhiyun #define PLLCTL_PLLENSRC_MASK BIT(5) 73*4882a593Smuzhiyun #define PLLCTL_PLLRST_SHIFT 3 74*4882a593Smuzhiyun #define PLLCTL_PLLRST_MASK BIT(3) 75*4882a593Smuzhiyun #define PLLCTL_PLLPWRDN_SHIFT 1 76*4882a593Smuzhiyun #define PLLCTL_PLLPWRDN_MASK BIT(1) 77*4882a593Smuzhiyun #define PLLCTL_PLLEN_SHIFT 0 78*4882a593Smuzhiyun #define PLLCTL_PLLEN_MASK BIT(0) 79*4882a593Smuzhiyun 80*4882a593Smuzhiyun /* SECCTL Bits */ 81*4882a593Smuzhiyun #define SECCTL_BYPASS_SHIFT 23 82*4882a593Smuzhiyun #define SECCTL_BYPASS_MASK BIT(23) 83*4882a593Smuzhiyun #define SECCTL_OP_DIV_SHIFT 19 84*4882a593Smuzhiyun #define SECCTL_OP_DIV_MASK (0xf << 19) 85*4882a593Smuzhiyun 86*4882a593Smuzhiyun /* PLLM Bits */ 87*4882a593Smuzhiyun #define PLLM_MULT_LO_SHIFT 0 88*4882a593Smuzhiyun #define PLLM_MULT_LO_MASK 0x3f 89*4882a593Smuzhiyun #define PLLM_MULT_LO_BITS 6 90*4882a593Smuzhiyun 91*4882a593Smuzhiyun /* PLLDIVn Bits */ 92*4882a593Smuzhiyun #define PLLDIV_ENABLE_SHIFT 15 93*4882a593Smuzhiyun #define PLLDIV_ENABLE_MASK BIT(15) 94*4882a593Smuzhiyun #define PLLDIV_RATIO_SHIFT 0x0 95*4882a593Smuzhiyun #define PLLDIV_RATIO_MASK 0xff 96*4882a593Smuzhiyun #define PLLDIV_MAX 16 97*4882a593Smuzhiyun 98*4882a593Smuzhiyun /* PLLCMD Bits */ 99*4882a593Smuzhiyun #define PLLCMD_GOSET_SHIFT 0 100*4882a593Smuzhiyun #define PLLCMD_GOSET_MASK BIT(0) 101*4882a593Smuzhiyun 102*4882a593Smuzhiyun /* PLLSTAT Bits */ 103*4882a593Smuzhiyun #define PLLSTAT_GOSTAT_SHIFT 0 104*4882a593Smuzhiyun #define PLLSTAT_GOSTAT_MASK BIT(0) 105*4882a593Smuzhiyun 106*4882a593Smuzhiyun /* Device Config PLLCTL0 */ 107*4882a593Smuzhiyun #define CFG_PLLCTL0_BWADJ_SHIFT 24 108*4882a593Smuzhiyun #define CFG_PLLCTL0_BWADJ_MASK (0xff << 24) 109*4882a593Smuzhiyun #define CFG_PLLCTL0_BWADJ_BITS 8 110*4882a593Smuzhiyun #define CFG_PLLCTL0_BYPASS_SHIFT 23 111*4882a593Smuzhiyun #define CFG_PLLCTL0_BYPASS_MASK BIT(23) 112*4882a593Smuzhiyun #define CFG_PLLCTL0_CLKOD_SHIFT 19 113*4882a593Smuzhiyun #define CFG_PLLCTL0_CLKOD_MASK (0xf << 19) 114*4882a593Smuzhiyun #define CFG_PLLCTL0_PLLM_HI_SHIFT 12 115*4882a593Smuzhiyun #define CFG_PLLCTL0_PLLM_HI_MASK (0x7f << 12) 116*4882a593Smuzhiyun #define CFG_PLLCTL0_PLLM_SHIFT 6 117*4882a593Smuzhiyun #define CFG_PLLCTL0_PLLM_MASK (0x1fff << 6) 118*4882a593Smuzhiyun #define CFG_PLLCTL0_PLLD_SHIFT 0 119*4882a593Smuzhiyun #define CFG_PLLCTL0_PLLD_MASK 0x3f 120*4882a593Smuzhiyun 121*4882a593Smuzhiyun /* Device Config PLLCTL1 */ 122*4882a593Smuzhiyun #define CFG_PLLCTL1_RST_SHIFT 14 123*4882a593Smuzhiyun #define CFG_PLLCTL1_RST_MASK BIT(14) 124*4882a593Smuzhiyun #define CFG_PLLCTL1_PAPLL_SHIFT 13 125*4882a593Smuzhiyun #define CFG_PLLCTL1_PAPLL_MASK BIT(13) 126*4882a593Smuzhiyun #define CFG_PLLCTL1_ENSAT_SHIFT 6 127*4882a593Smuzhiyun #define CFG_PLLCTL1_ENSAT_MASK BIT(6) 128*4882a593Smuzhiyun #define CFG_PLLCTL1_BWADJ_SHIFT 0 129*4882a593Smuzhiyun #define CFG_PLLCTL1_BWADJ_MASK 0xf 130*4882a593Smuzhiyun 131*4882a593Smuzhiyun #define MISC_CTL1_ARM_PLL_EN BIT(13) 132*4882a593Smuzhiyun 133*4882a593Smuzhiyun #endif /* _CLOCK_DEFS_H_ */ 134