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Searched refs:ddrclk (Results 1 – 5 of 5) sorted by relevance

/OK3568_Linux_fs/kernel/drivers/clk/rockchip/
H A Dclk-ddr.c101 struct rockchip_ddrclk *ddrclk = to_rockchip_ddrclk_hw(hw); in rockchip_ddrclk_get_parent() local
104 val = readl(ddrclk->reg_base + in rockchip_ddrclk_get_parent()
105 ddrclk->mux_offset) >> ddrclk->mux_shift; in rockchip_ddrclk_get_parent()
106 val &= GENMASK(ddrclk->mux_width - 1, 0); in rockchip_ddrclk_get_parent()
186 struct rockchip_ddrclk *ddrclk; in rockchip_clk_register_ddrclk() local
195 ddrclk = kzalloc(sizeof(*ddrclk), GFP_KERNEL); in rockchip_clk_register_ddrclk()
196 if (!ddrclk) in rockchip_clk_register_ddrclk()
219 kfree(ddrclk); in rockchip_clk_register_ddrclk()
223 ddrclk->reg_base = reg_base; in rockchip_clk_register_ddrclk()
224 ddrclk->hw.init = &init; in rockchip_clk_register_ddrclk()
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/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/clock/
H A Dmvebu-core-clock.txt18 3 = ddrclk (DDR clock)
24 3 = ddrclk (DDR clock)
37 2 = ddrclk (DDR clock)
44 3 = ddrclk (DDR controller clock derived from CPU0 clock)
49 2 = ddrclk (DDR controller clock derived from CPU0 clock)
72 output names ("tclk", "cpuclk", "l2clk", "ddrclk")
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/arm/marvell/
H A Dkirkwood.txt12 cpus/cpu@0 with three clocks, "cpu_clk", "ddrclk" and "powersave",
14 between the "cpu_clk" and the "ddrclk".
26 clock-names = "cpu_clk", "ddrclk", "powersave";
/OK3568_Linux_fs/u-boot/arch/mips/mach-ath79/ar934x/
H A Dclk.c264 u32 cpuclk, ddrclk, busclk; in ar934x_update_clock() local
284 ddrclk = ar934x_get_xtal(); in ar934x_update_clock()
286 ddrclk = ddrpll; in ar934x_update_clock()
288 ddrclk = cpupll; in ar934x_update_clock()
305 gd->mem_clk = ddrclk / (ddrdiv + 1); in ar934x_update_clock()
/OK3568_Linux_fs/kernel/arch/arm/boot/dts/
H A Dkirkwood.dtsi22 clock-names = "cpu_clk", "ddrclk", "powersave";