Searched refs:ddrc_base (Results 1 – 4 of 4) sorted by relevance
23 static void __iomem *ddrc_base; variable58 ddrc_base = zynq_pm_ioremap("xlnx,zynq-ddrc-a05"); in zynq_pm_late_init()59 if (!ddrc_base) { in zynq_pm_late_init()67 reg = readl(ddrc_base + DDRC_DRAM_PARAM_REG3_OFFS); in zynq_pm_late_init()69 writel(reg, ddrc_base + DDRC_DRAM_PARAM_REG3_OFFS); in zynq_pm_late_init()
31 width = readl(&ddrc_base->ddrc_ctrl); in zynq_ddrc_init()34 ecctype = (readl(&ddrc_base->ecc_scrub) & in zynq_ddrc_init()
94 static void __iomem *ddrc_base; variable569 ddr_data.ddrc_pwrctrl = readl_relaxed(ddrc_base + 0x30); in ddr_sleep_config()573 ddr_data.ddrc_dfilpcfg0 = readl_relaxed(ddrc_base + 0x198); in ddr_sleep_config()576 val = readl_relaxed(ddrc_base + 0x30); in ddr_sleep_config()577 writel_relaxed(val & ~(BIT(0) | BIT(1)), ddrc_base + 0x30); in ddr_sleep_config()587 while ((readl_relaxed(ddrc_base + 0x4) & 0x7) != 0x1) in ddr_sleep_config()590 val = readl_relaxed(ddrc_base + 0x198) & ~(0xf << 12 | 0xf << 4); in ddr_sleep_config()592 writel_relaxed(val, ddrc_base + 0x198); in ddr_sleep_config()594 val = readl_relaxed(ddrc_base + 0x198) | BIT(8) | BIT(0); in ddr_sleep_config()595 writel_relaxed(val, ddrc_base + 0x198); in ddr_sleep_config()[all …]
132 #define ddrc_base ((struct ddrc_regs *)ZYNQ_DDRC_BASEADDR) macro