94 static void __iomem *ddrc_base;  variable
569 	ddr_data.ddrc_pwrctrl = readl_relaxed(ddrc_base + 0x30);  in ddr_sleep_config()
573 	ddr_data.ddrc_dfilpcfg0 = readl_relaxed(ddrc_base + 0x198);  in ddr_sleep_config()
576 	val = readl_relaxed(ddrc_base + 0x30);  in ddr_sleep_config()
577 	writel_relaxed(val & ~(BIT(0) | BIT(1)), ddrc_base + 0x30);  in ddr_sleep_config()
587 	while ((readl_relaxed(ddrc_base + 0x4) & 0x7) != 0x1)  in ddr_sleep_config()
590 	val = readl_relaxed(ddrc_base + 0x198) & ~(0xf << 12 | 0xf << 4);  in ddr_sleep_config()
592 	writel_relaxed(val, ddrc_base + 0x198);  in ddr_sleep_config()
594 	val = readl_relaxed(ddrc_base + 0x198) | BIT(8) | BIT(0);  in ddr_sleep_config()
595 	writel_relaxed(val, ddrc_base + 0x198);  in ddr_sleep_config()
1038 	ddrc_base = dev_reg_base + RV1106_DDRC_OFFSET;  in rv1106_suspend_init()