Searched refs:ddr_in32 (Results 1 – 7 of 7) sorted by relevance
27 while (ddr_in32(ptr) & bits) { in set_wait_for_bits_clear()235 temp32 = ddr_in32(&ddr->debug[28]); in fsl_ddr_set_memctl_regs()258 temp32 = ddr_in32(&ddr->debug[25]); in fsl_ddr_set_memctl_regs()267 temp32 = ddr_in32(&ddr->debug[28]); in fsl_ddr_set_memctl_regs()303 temp32 = ddr_in32(&ddr->sdram_cfg_2); in fsl_ddr_set_memctl_regs()309 temp32 = (ddr_in32(&ddr->sdram_cfg) | SDRAM_CFG_BI); in fsl_ddr_set_memctl_regs()312 temp32 = ddr_in32(&ddr->sdram_cfg) & ~SDRAM_CFG_BI; in fsl_ddr_set_memctl_regs()323 while (!(ddr_in32(&ddr->debug[1]) & 0x2) && in fsl_ddr_set_memctl_regs()330 ctrl_num, ddr_in32(&ddr->debug[1])); in fsl_ddr_set_memctl_regs()367 temp32 = ddr_in32(&ddr->debug[28]); in fsl_ddr_set_memctl_regs()[all …]
56 ver_major_minor_errata = (ddr_in32(&ddr->ip_rev1) & 0xFFFF) << 8; in fsl_ddr_get_version()57 ver_major_minor_errata |= (ddr_in32(&ddr->ip_rev2) & 0xFF00) >> 8; in fsl_ddr_get_version()185 uint32_t cs0_config = ddr_in32(&ddr->cs0_config); in print_ddr_info()187 uint32_t sdram_cfg = ddr_in32(&ddr->sdram_cfg); in print_ddr_info()194 sdram_cfg = ddr_in32(&ddr->sdram_cfg); in print_ddr_info()201 sdram_cfg = ddr_in32(&ddr->sdram_cfg); in print_ddr_info()238 cas_lat = ((ddr_in32(&ddr->timing_cfg_1) >> 16) & 0xf); in print_ddr_info()243 cas_lat += ((ddr_in32(&ddr->timing_cfg_3) >> 12) & 3) << 4; in print_ddr_info()372 ddrc_debug20 = ddr_in32(&ddr->debug[19]); in fsl_ddr_sync_memctl_refresh()377 ddrc_debug20 = ddr_in32(&ddr->debug[19]); in fsl_ddr_sync_memctl_refresh()[all …]
187 temp_sdram_cfg = ddr_in32(&ddr->sdram_cfg_2); in fsl_ddr_set_memctl_regs()193 temp_sdram_cfg = (ddr_in32(&ddr->sdram_cfg) | SDRAM_CFG_BI); in fsl_ddr_set_memctl_regs()196 temp_sdram_cfg = ddr_in32(&ddr->sdram_cfg) & ~SDRAM_CFG_BI; in fsl_ddr_set_memctl_regs()223 bus_width = 3 - ((ddr_in32(&ddr->sdram_cfg) & SDRAM_CFG_DBW_MASK) in fsl_ddr_set_memctl_regs()232 while ((ddr_in32(&ddr->sdram_cfg_2) & SDRAM_CFG2_D_INIT) && in fsl_ddr_set_memctl_regs()243 temp_sdram_cfg = ddr_in32(&ddr->sdram_cfg_2); in fsl_ddr_set_memctl_regs()
2572 ddr->debug[28] = ddr_in32(&ddrc->debug[28]); in compute_fsl_memctl_config_regs()2580 ddr->debug[28] |= ddr_in32(&ddrc->debug[28]); in compute_fsl_memctl_config_regs()2610 u32 cpo_min = ddr_in32(&ddr->debug[9]) >> 24; in erratum_a009942_check_cpo()2615 sdram_cfg = ddr_in32(&ddr->sdram_cfg); in erratum_a009942_check_cpo()2628 cpo = ddr_in32(&ddr->debug[i]); in erratum_a009942_check_cpo()2640 cpo = ddr_in32(&ddr->debug[13]); in erratum_a009942_check_cpo()2648 cpo_target = ddr_in32(&ddr->debug[28]) & 0xff; in erratum_a009942_check_cpo()
41 static inline u32 ddr_in32(void __iomem *addr) in ddr_in32() function66 ddr_in32(pdata->mc_vbase + FSL_MC_DATA_ERR_INJECT_HI)); in fsl_mc_inject_data_hi_show()76 ddr_in32(pdata->mc_vbase + FSL_MC_DATA_ERR_INJECT_LO)); in fsl_mc_inject_data_lo_show()86 ddr_in32(pdata->mc_vbase + FSL_MC_ECC_ERR_INJECT)); in fsl_mc_inject_ctrl_show()292 err_detect = ddr_in32(pdata->mc_vbase + FSL_MC_ERR_DETECT); in fsl_mc_check()305 syndrome = ddr_in32(pdata->mc_vbase + FSL_MC_CAPTURE_ECC); in fsl_mc_check()308 bus_width = (ddr_in32(pdata->mc_vbase + FSL_MC_DDR_SDRAM_CFG) & in fsl_mc_check()316 ddr_in32(pdata->mc_vbase + FSL_MC_CAPTURE_EXT_ADDRESS), in fsl_mc_check()317 ddr_in32(pdata->mc_vbase + FSL_MC_CAPTURE_ADDRESS)); in fsl_mc_check()326 cap_high = ddr_in32(pdata->mc_vbase + FSL_MC_CAPTURE_DATA_HI); in fsl_mc_check()[all …]
22 #define ddr_in32(a) in_le32(a) macro28 #define ddr_in32(a) in_be32(a) macro
319 tmp = ddr_in32(&ddr->eor); in erratum_a008850_post()405 tmp = ddr_in32(&ddr->ddr_cdr1); in ddr_enable_0v9_volt()