Searched refs:UTMIP_PLL_CFG1 (Results 1 – 3 of 3) sorted by relevance
183 #define UTMIP_PLL_CFG1 0x484 macro1171 value = readl_relaxed(pll->clk_base + UTMIP_PLL_CFG1); in clk_pllu_enable()1181 writel_relaxed(value, pll->clk_base + UTMIP_PLL_CFG1); in clk_pllu_enable()1794 value = readl_relaxed(pll->clk_base + UTMIP_PLL_CFG1); in clk_pllu_tegra114_enable()1805 writel_relaxed(value, pll->clk_base + UTMIP_PLL_CFG1); in clk_pllu_tegra114_enable()1814 value = readl_relaxed(pll->clk_base + UTMIP_PLL_CFG1); in clk_pllu_tegra114_enable()1817 writel_relaxed(value, pll->clk_base + UTMIP_PLL_CFG1); in clk_pllu_tegra114_enable()
170 #define UTMIP_PLL_CFG1 0x484 macro2785 reg = readl_relaxed(clk_base + UTMIP_PLL_CFG1); in tegra210_utmi_param_configure()2796 writel_relaxed(reg, clk_base + UTMIP_PLL_CFG1); in tegra210_utmi_param_configure()2799 reg = readl_relaxed(clk_base + UTMIP_PLL_CFG1); in tegra210_utmi_param_configure()2802 writel_relaxed(reg, clk_base + UTMIP_PLL_CFG1); in tegra210_utmi_param_configure()2817 reg = readl_relaxed(clk_base + UTMIP_PLL_CFG1); in tegra210_utmi_param_configure()2820 writel_relaxed(reg, clk_base + UTMIP_PLL_CFG1); in tegra210_utmi_param_configure()
80 #define UTMIP_PLL_CFG1 0x804 macro498 val = readl_relaxed(base + UTMIP_PLL_CFG1); in utmi_phy_power_on()503 writel_relaxed(val, base + UTMIP_PLL_CFG1); in utmi_phy_power_on()