Searched refs:TEGRA210_CLK_PLL_C4_OUT0 (Results 1 – 5 of 5) sorted by relevance
338 #define TEGRA210_CLK_PLL_C4_OUT0 308 macro
342 #define TEGRA210_CLK_PLL_C4_OUT0 308 macro
145 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>;1218 <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>,1220 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>;1284 <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>;1285 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>;
2483 [tegra_clk_pll_c4_out0] = { .dt_id = TEGRA210_CLK_PLL_C4_OUT0, .present = true },2568 { .con_id = "pll_c4_out0", .dt_id = TEGRA210_CLK_PLL_C4_OUT0 },3322 clks[TEGRA210_CLK_PLL_C4_OUT0] = clk; in tegra210_pll_init()
381 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>;