1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * This header provides constants for binding nvidia,tegra210-car. 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * The first 224 clocks are numbered to match the bits in the CAR's CLK_OUT_ENB 6*4882a593Smuzhiyun * registers. These IDs often match those in the CAR's RST_DEVICES registers, 7*4882a593Smuzhiyun * but not in all cases. Some bits in CLK_OUT_ENB affect multiple clocks. In 8*4882a593Smuzhiyun * this case, those clocks are assigned IDs above 224 in order to highlight 9*4882a593Smuzhiyun * this issue. Implementations that interpret these clock IDs as bit values 10*4882a593Smuzhiyun * within the CLK_OUT_ENB or RST_DEVICES registers should be careful to 11*4882a593Smuzhiyun * explicitly handle these special cases. 12*4882a593Smuzhiyun * 13*4882a593Smuzhiyun * The balance of the clocks controlled by the CAR are assigned IDs of 224 and 14*4882a593Smuzhiyun * above. 15*4882a593Smuzhiyun */ 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun #ifndef _DT_BINDINGS_CLOCK_TEGRA210_CAR_H 18*4882a593Smuzhiyun #define _DT_BINDINGS_CLOCK_TEGRA210_CAR_H 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun /* 0 */ 21*4882a593Smuzhiyun /* 1 */ 22*4882a593Smuzhiyun /* 2 */ 23*4882a593Smuzhiyun #define TEGRA210_CLK_ISPB 3 24*4882a593Smuzhiyun #define TEGRA210_CLK_RTC 4 25*4882a593Smuzhiyun #define TEGRA210_CLK_TIMER 5 26*4882a593Smuzhiyun #define TEGRA210_CLK_UARTA 6 27*4882a593Smuzhiyun /* 7 (register bit affects uartb and vfir) */ 28*4882a593Smuzhiyun #define TEGRA210_CLK_GPIO 8 29*4882a593Smuzhiyun #define TEGRA210_CLK_SDMMC2 9 30*4882a593Smuzhiyun /* 10 (register bit affects spdif_in and spdif_out) */ 31*4882a593Smuzhiyun #define TEGRA210_CLK_I2S1 11 32*4882a593Smuzhiyun #define TEGRA210_CLK_I2C1 12 33*4882a593Smuzhiyun /* 13 */ 34*4882a593Smuzhiyun #define TEGRA210_CLK_SDMMC1 14 35*4882a593Smuzhiyun #define TEGRA210_CLK_SDMMC4 15 36*4882a593Smuzhiyun /* 16 */ 37*4882a593Smuzhiyun #define TEGRA210_CLK_PWM 17 38*4882a593Smuzhiyun #define TEGRA210_CLK_I2S2 18 39*4882a593Smuzhiyun /* 19 */ 40*4882a593Smuzhiyun /* 20 (register bit affects vi and vi_sensor) */ 41*4882a593Smuzhiyun /* 21 */ 42*4882a593Smuzhiyun #define TEGRA210_CLK_USBD 22 43*4882a593Smuzhiyun #define TEGRA210_CLK_ISPA 23 44*4882a593Smuzhiyun /* 24 */ 45*4882a593Smuzhiyun /* 25 */ 46*4882a593Smuzhiyun #define TEGRA210_CLK_DISP2 26 47*4882a593Smuzhiyun #define TEGRA210_CLK_DISP1 27 48*4882a593Smuzhiyun #define TEGRA210_CLK_HOST1X 28 49*4882a593Smuzhiyun /* 29 */ 50*4882a593Smuzhiyun #define TEGRA210_CLK_I2S0 30 51*4882a593Smuzhiyun /* 31 */ 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun #define TEGRA210_CLK_MC 32 54*4882a593Smuzhiyun #define TEGRA210_CLK_AHBDMA 33 55*4882a593Smuzhiyun #define TEGRA210_CLK_APBDMA 34 56*4882a593Smuzhiyun /* 35 */ 57*4882a593Smuzhiyun /* 36 */ 58*4882a593Smuzhiyun /* 37 */ 59*4882a593Smuzhiyun #define TEGRA210_CLK_PMC 38 60*4882a593Smuzhiyun /* 39 (register bit affects fuse and fuse_burn) */ 61*4882a593Smuzhiyun #define TEGRA210_CLK_KFUSE 40 62*4882a593Smuzhiyun #define TEGRA210_CLK_SBC1 41 63*4882a593Smuzhiyun /* 42 */ 64*4882a593Smuzhiyun /* 43 */ 65*4882a593Smuzhiyun #define TEGRA210_CLK_SBC2 44 66*4882a593Smuzhiyun /* 45 */ 67*4882a593Smuzhiyun #define TEGRA210_CLK_SBC3 46 68*4882a593Smuzhiyun #define TEGRA210_CLK_I2C5 47 69*4882a593Smuzhiyun #define TEGRA210_CLK_DSIA 48 70*4882a593Smuzhiyun /* 49 */ 71*4882a593Smuzhiyun /* 50 */ 72*4882a593Smuzhiyun /* 51 */ 73*4882a593Smuzhiyun #define TEGRA210_CLK_CSI 52 74*4882a593Smuzhiyun /* 53 */ 75*4882a593Smuzhiyun #define TEGRA210_CLK_I2C2 54 76*4882a593Smuzhiyun #define TEGRA210_CLK_UARTC 55 77*4882a593Smuzhiyun #define TEGRA210_CLK_MIPI_CAL 56 78*4882a593Smuzhiyun #define TEGRA210_CLK_EMC 57 79*4882a593Smuzhiyun #define TEGRA210_CLK_USB2 58 80*4882a593Smuzhiyun /* 59 */ 81*4882a593Smuzhiyun /* 60 */ 82*4882a593Smuzhiyun /* 61 */ 83*4882a593Smuzhiyun /* 62 */ 84*4882a593Smuzhiyun #define TEGRA210_CLK_BSEV 63 85*4882a593Smuzhiyun 86*4882a593Smuzhiyun /* 64 */ 87*4882a593Smuzhiyun #define TEGRA210_CLK_UARTD 65 88*4882a593Smuzhiyun /* 66 */ 89*4882a593Smuzhiyun #define TEGRA210_CLK_I2C3 67 90*4882a593Smuzhiyun #define TEGRA210_CLK_SBC4 68 91*4882a593Smuzhiyun #define TEGRA210_CLK_SDMMC3 69 92*4882a593Smuzhiyun #define TEGRA210_CLK_PCIE 70 93*4882a593Smuzhiyun #define TEGRA210_CLK_OWR 71 94*4882a593Smuzhiyun #define TEGRA210_CLK_AFI 72 95*4882a593Smuzhiyun #define TEGRA210_CLK_CSITE 73 96*4882a593Smuzhiyun /* 74 */ 97*4882a593Smuzhiyun /* 75 */ 98*4882a593Smuzhiyun #define TEGRA210_CLK_LA 76 99*4882a593Smuzhiyun /* 77 */ 100*4882a593Smuzhiyun #define TEGRA210_CLK_SOC_THERM 78 101*4882a593Smuzhiyun #define TEGRA210_CLK_DTV 79 102*4882a593Smuzhiyun /* 80 */ 103*4882a593Smuzhiyun #define TEGRA210_CLK_I2CSLOW 81 104*4882a593Smuzhiyun #define TEGRA210_CLK_DSIB 82 105*4882a593Smuzhiyun #define TEGRA210_CLK_TSEC 83 106*4882a593Smuzhiyun /* 84 */ 107*4882a593Smuzhiyun /* 85 */ 108*4882a593Smuzhiyun /* 86 */ 109*4882a593Smuzhiyun /* 87 */ 110*4882a593Smuzhiyun /* 88 */ 111*4882a593Smuzhiyun #define TEGRA210_CLK_XUSB_HOST 89 112*4882a593Smuzhiyun /* 90 */ 113*4882a593Smuzhiyun /* 91 */ 114*4882a593Smuzhiyun #define TEGRA210_CLK_CSUS 92 115*4882a593Smuzhiyun /* 93 */ 116*4882a593Smuzhiyun /* 94 */ 117*4882a593Smuzhiyun /* 95 (bit affects xusb_dev and xusb_dev_src) */ 118*4882a593Smuzhiyun 119*4882a593Smuzhiyun /* 96 */ 120*4882a593Smuzhiyun /* 97 */ 121*4882a593Smuzhiyun /* 98 */ 122*4882a593Smuzhiyun #define TEGRA210_CLK_MSELECT 99 123*4882a593Smuzhiyun #define TEGRA210_CLK_TSENSOR 100 124*4882a593Smuzhiyun #define TEGRA210_CLK_I2S3 101 125*4882a593Smuzhiyun #define TEGRA210_CLK_I2S4 102 126*4882a593Smuzhiyun #define TEGRA210_CLK_I2C4 103 127*4882a593Smuzhiyun /* 104 */ 128*4882a593Smuzhiyun /* 105 */ 129*4882a593Smuzhiyun #define TEGRA210_CLK_D_AUDIO 106 130*4882a593Smuzhiyun #define TEGRA210_CLK_APB2APE 107 131*4882a593Smuzhiyun /* 108 */ 132*4882a593Smuzhiyun /* 109 */ 133*4882a593Smuzhiyun /* 110 */ 134*4882a593Smuzhiyun #define TEGRA210_CLK_HDA2CODEC_2X 111 135*4882a593Smuzhiyun /* 112 */ 136*4882a593Smuzhiyun /* 113 */ 137*4882a593Smuzhiyun /* 114 */ 138*4882a593Smuzhiyun /* 115 */ 139*4882a593Smuzhiyun /* 116 */ 140*4882a593Smuzhiyun /* 117 */ 141*4882a593Smuzhiyun #define TEGRA210_CLK_SPDIF_2X 118 142*4882a593Smuzhiyun #define TEGRA210_CLK_ACTMON 119 143*4882a593Smuzhiyun #define TEGRA210_CLK_EXTERN1 120 144*4882a593Smuzhiyun #define TEGRA210_CLK_EXTERN2 121 145*4882a593Smuzhiyun #define TEGRA210_CLK_EXTERN3 122 146*4882a593Smuzhiyun #define TEGRA210_CLK_SATA_OOB 123 147*4882a593Smuzhiyun #define TEGRA210_CLK_SATA 124 148*4882a593Smuzhiyun #define TEGRA210_CLK_HDA 125 149*4882a593Smuzhiyun /* 126 */ 150*4882a593Smuzhiyun /* 127 */ 151*4882a593Smuzhiyun 152*4882a593Smuzhiyun #define TEGRA210_CLK_HDA2HDMI 128 153*4882a593Smuzhiyun /* 129 */ 154*4882a593Smuzhiyun /* 130 */ 155*4882a593Smuzhiyun /* 131 */ 156*4882a593Smuzhiyun /* 132 */ 157*4882a593Smuzhiyun /* 133 */ 158*4882a593Smuzhiyun /* 134 */ 159*4882a593Smuzhiyun /* 135 */ 160*4882a593Smuzhiyun #define TEGRA210_CLK_CEC 136 161*4882a593Smuzhiyun /* 137 */ 162*4882a593Smuzhiyun /* 138 */ 163*4882a593Smuzhiyun /* 139 */ 164*4882a593Smuzhiyun /* 140 */ 165*4882a593Smuzhiyun /* 141 */ 166*4882a593Smuzhiyun /* 142 */ 167*4882a593Smuzhiyun /* (bit affects xusb_falcon_src, xusb_fs_src, xusb_host_src and xusb_ss_src) */ 168*4882a593Smuzhiyun #define TEGRA210_CLK_XUSB_GATE 143 169*4882a593Smuzhiyun #define TEGRA210_CLK_CILAB 144 170*4882a593Smuzhiyun #define TEGRA210_CLK_CILCD 145 171*4882a593Smuzhiyun #define TEGRA210_CLK_CILE 146 172*4882a593Smuzhiyun #define TEGRA210_CLK_DSIALP 147 173*4882a593Smuzhiyun #define TEGRA210_CLK_DSIBLP 148 174*4882a593Smuzhiyun #define TEGRA210_CLK_ENTROPY 149 175*4882a593Smuzhiyun /* 150 */ 176*4882a593Smuzhiyun /* 151 */ 177*4882a593Smuzhiyun #define TEGRA210_CLK_DP2 152 178*4882a593Smuzhiyun /* 153 */ 179*4882a593Smuzhiyun /* 154 */ 180*4882a593Smuzhiyun /* 155 (bit affects dfll_ref and dfll_soc) */ 181*4882a593Smuzhiyun #define TEGRA210_CLK_XUSB_SS 156 182*4882a593Smuzhiyun /* 157 */ 183*4882a593Smuzhiyun /* 158 */ 184*4882a593Smuzhiyun /* 159 */ 185*4882a593Smuzhiyun 186*4882a593Smuzhiyun /* 160 */ 187*4882a593Smuzhiyun #define TEGRA210_CLK_DMIC1 161 188*4882a593Smuzhiyun #define TEGRA210_CLK_DMIC2 162 189*4882a593Smuzhiyun /* 163 */ 190*4882a593Smuzhiyun /* 164 */ 191*4882a593Smuzhiyun /* 165 */ 192*4882a593Smuzhiyun #define TEGRA210_CLK_I2C6 166 193*4882a593Smuzhiyun /* 167 */ 194*4882a593Smuzhiyun /* 168 */ 195*4882a593Smuzhiyun /* 169 */ 196*4882a593Smuzhiyun /* 170 */ 197*4882a593Smuzhiyun #define TEGRA210_CLK_VIM2_CLK 171 198*4882a593Smuzhiyun /* 172 */ 199*4882a593Smuzhiyun #define TEGRA210_CLK_MIPIBIF 173 200*4882a593Smuzhiyun /* 174 */ 201*4882a593Smuzhiyun /* 175 */ 202*4882a593Smuzhiyun /* 176 */ 203*4882a593Smuzhiyun #define TEGRA210_CLK_CLK72MHZ 177 204*4882a593Smuzhiyun #define TEGRA210_CLK_VIC03 178 205*4882a593Smuzhiyun /* 179 */ 206*4882a593Smuzhiyun /* 180 */ 207*4882a593Smuzhiyun #define TEGRA210_CLK_DPAUX 181 208*4882a593Smuzhiyun #define TEGRA210_CLK_SOR0 182 209*4882a593Smuzhiyun #define TEGRA210_CLK_SOR1 183 210*4882a593Smuzhiyun #define TEGRA210_CLK_GPU 184 211*4882a593Smuzhiyun #define TEGRA210_CLK_DBGAPB 185 212*4882a593Smuzhiyun /* 186 */ 213*4882a593Smuzhiyun #define TEGRA210_CLK_PLL_P_OUT_ADSP 187 214*4882a593Smuzhiyun /* 188 ((bit affects pll_a_out_adsp and pll_a_out0_out_adsp)*/ 215*4882a593Smuzhiyun #define TEGRA210_CLK_PLL_G_REF 189 216*4882a593Smuzhiyun /* 190 */ 217*4882a593Smuzhiyun /* 191 */ 218*4882a593Smuzhiyun 219*4882a593Smuzhiyun /* 192 */ 220*4882a593Smuzhiyun #define TEGRA210_CLK_SDMMC_LEGACY 193 221*4882a593Smuzhiyun #define TEGRA210_CLK_NVDEC 194 222*4882a593Smuzhiyun #define TEGRA210_CLK_NVJPG 195 223*4882a593Smuzhiyun /* 196 */ 224*4882a593Smuzhiyun #define TEGRA210_CLK_DMIC3 197 225*4882a593Smuzhiyun #define TEGRA210_CLK_APE 198 226*4882a593Smuzhiyun #define TEGRA210_CLK_ADSP 199 227*4882a593Smuzhiyun /* 200 */ 228*4882a593Smuzhiyun /* 201 */ 229*4882a593Smuzhiyun #define TEGRA210_CLK_MAUD 202 230*4882a593Smuzhiyun /* 203 */ 231*4882a593Smuzhiyun /* 204 */ 232*4882a593Smuzhiyun /* 205 */ 233*4882a593Smuzhiyun #define TEGRA210_CLK_TSECB 206 234*4882a593Smuzhiyun #define TEGRA210_CLK_DPAUX1 207 235*4882a593Smuzhiyun #define TEGRA210_CLK_VI_I2C 208 236*4882a593Smuzhiyun #define TEGRA210_CLK_HSIC_TRK 209 237*4882a593Smuzhiyun #define TEGRA210_CLK_USB2_TRK 210 238*4882a593Smuzhiyun #define TEGRA210_CLK_QSPI 211 239*4882a593Smuzhiyun #define TEGRA210_CLK_UARTAPE 212 240*4882a593Smuzhiyun /* 213 */ 241*4882a593Smuzhiyun /* 214 */ 242*4882a593Smuzhiyun /* 215 */ 243*4882a593Smuzhiyun /* 216 */ 244*4882a593Smuzhiyun /* 217 */ 245*4882a593Smuzhiyun #define TEGRA210_CLK_ADSP_NEON 218 246*4882a593Smuzhiyun #define TEGRA210_CLK_NVENC 219 247*4882a593Smuzhiyun #define TEGRA210_CLK_IQC2 220 248*4882a593Smuzhiyun #define TEGRA210_CLK_IQC1 221 249*4882a593Smuzhiyun #define TEGRA210_CLK_SOR_SAFE 222 250*4882a593Smuzhiyun #define TEGRA210_CLK_PLL_P_OUT_CPU 223 251*4882a593Smuzhiyun 252*4882a593Smuzhiyun 253*4882a593Smuzhiyun #define TEGRA210_CLK_UARTB 224 254*4882a593Smuzhiyun #define TEGRA210_CLK_VFIR 225 255*4882a593Smuzhiyun #define TEGRA210_CLK_SPDIF_IN 226 256*4882a593Smuzhiyun #define TEGRA210_CLK_SPDIF_OUT 227 257*4882a593Smuzhiyun #define TEGRA210_CLK_VI 228 258*4882a593Smuzhiyun #define TEGRA210_CLK_VI_SENSOR 229 259*4882a593Smuzhiyun #define TEGRA210_CLK_FUSE 230 260*4882a593Smuzhiyun #define TEGRA210_CLK_FUSE_BURN 231 261*4882a593Smuzhiyun #define TEGRA210_CLK_CLK_32K 232 262*4882a593Smuzhiyun #define TEGRA210_CLK_CLK_M 233 263*4882a593Smuzhiyun #define TEGRA210_CLK_CLK_M_DIV2 234 264*4882a593Smuzhiyun #define TEGRA210_CLK_CLK_M_DIV4 235 265*4882a593Smuzhiyun #define TEGRA210_CLK_OSC_DIV2 234 266*4882a593Smuzhiyun #define TEGRA210_CLK_OSC_DIV4 235 267*4882a593Smuzhiyun #define TEGRA210_CLK_PLL_REF 236 268*4882a593Smuzhiyun #define TEGRA210_CLK_PLL_C 237 269*4882a593Smuzhiyun #define TEGRA210_CLK_PLL_C_OUT1 238 270*4882a593Smuzhiyun #define TEGRA210_CLK_PLL_C2 239 271*4882a593Smuzhiyun #define TEGRA210_CLK_PLL_C3 240 272*4882a593Smuzhiyun #define TEGRA210_CLK_PLL_M 241 273*4882a593Smuzhiyun #define TEGRA210_CLK_PLL_M_OUT1 242 274*4882a593Smuzhiyun #define TEGRA210_CLK_PLL_P 243 275*4882a593Smuzhiyun #define TEGRA210_CLK_PLL_P_OUT1 244 276*4882a593Smuzhiyun #define TEGRA210_CLK_PLL_P_OUT2 245 277*4882a593Smuzhiyun #define TEGRA210_CLK_PLL_P_OUT3 246 278*4882a593Smuzhiyun #define TEGRA210_CLK_PLL_P_OUT4 247 279*4882a593Smuzhiyun #define TEGRA210_CLK_PLL_A 248 280*4882a593Smuzhiyun #define TEGRA210_CLK_PLL_A_OUT0 249 281*4882a593Smuzhiyun #define TEGRA210_CLK_PLL_D 250 282*4882a593Smuzhiyun #define TEGRA210_CLK_PLL_D_OUT0 251 283*4882a593Smuzhiyun #define TEGRA210_CLK_PLL_D2 252 284*4882a593Smuzhiyun #define TEGRA210_CLK_PLL_D2_OUT0 253 285*4882a593Smuzhiyun #define TEGRA210_CLK_PLL_U 254 286*4882a593Smuzhiyun #define TEGRA210_CLK_PLL_U_480M 255 287*4882a593Smuzhiyun 288*4882a593Smuzhiyun #define TEGRA210_CLK_PLL_U_60M 256 289*4882a593Smuzhiyun #define TEGRA210_CLK_PLL_U_48M 257 290*4882a593Smuzhiyun /* 258 */ 291*4882a593Smuzhiyun #define TEGRA210_CLK_PLL_X 259 292*4882a593Smuzhiyun #define TEGRA210_CLK_PLL_X_OUT0 260 293*4882a593Smuzhiyun #define TEGRA210_CLK_PLL_RE_VCO 261 294*4882a593Smuzhiyun #define TEGRA210_CLK_PLL_RE_OUT 262 295*4882a593Smuzhiyun #define TEGRA210_CLK_PLL_E 263 296*4882a593Smuzhiyun #define TEGRA210_CLK_SPDIF_IN_SYNC 264 297*4882a593Smuzhiyun #define TEGRA210_CLK_I2S0_SYNC 265 298*4882a593Smuzhiyun #define TEGRA210_CLK_I2S1_SYNC 266 299*4882a593Smuzhiyun #define TEGRA210_CLK_I2S2_SYNC 267 300*4882a593Smuzhiyun #define TEGRA210_CLK_I2S3_SYNC 268 301*4882a593Smuzhiyun #define TEGRA210_CLK_I2S4_SYNC 269 302*4882a593Smuzhiyun #define TEGRA210_CLK_VIMCLK_SYNC 270 303*4882a593Smuzhiyun #define TEGRA210_CLK_AUDIO0 271 304*4882a593Smuzhiyun #define TEGRA210_CLK_AUDIO1 272 305*4882a593Smuzhiyun #define TEGRA210_CLK_AUDIO2 273 306*4882a593Smuzhiyun #define TEGRA210_CLK_AUDIO3 274 307*4882a593Smuzhiyun #define TEGRA210_CLK_AUDIO4 275 308*4882a593Smuzhiyun #define TEGRA210_CLK_SPDIF 276 309*4882a593Smuzhiyun /* 277 */ 310*4882a593Smuzhiyun /* 278 */ 311*4882a593Smuzhiyun /* 279 */ 312*4882a593Smuzhiyun /* 280 */ 313*4882a593Smuzhiyun #define TEGRA210_CLK_SOR0_LVDS 281 /* deprecated */ 314*4882a593Smuzhiyun #define TEGRA210_CLK_SOR0_OUT 281 315*4882a593Smuzhiyun #define TEGRA210_CLK_SOR1_OUT 282 316*4882a593Smuzhiyun /* 283 */ 317*4882a593Smuzhiyun #define TEGRA210_CLK_XUSB_HOST_SRC 284 318*4882a593Smuzhiyun #define TEGRA210_CLK_XUSB_FALCON_SRC 285 319*4882a593Smuzhiyun #define TEGRA210_CLK_XUSB_FS_SRC 286 320*4882a593Smuzhiyun #define TEGRA210_CLK_XUSB_SS_SRC 287 321*4882a593Smuzhiyun 322*4882a593Smuzhiyun #define TEGRA210_CLK_XUSB_DEV_SRC 288 323*4882a593Smuzhiyun #define TEGRA210_CLK_XUSB_DEV 289 324*4882a593Smuzhiyun #define TEGRA210_CLK_XUSB_HS_SRC 290 325*4882a593Smuzhiyun #define TEGRA210_CLK_SCLK 291 326*4882a593Smuzhiyun #define TEGRA210_CLK_HCLK 292 327*4882a593Smuzhiyun #define TEGRA210_CLK_PCLK 293 328*4882a593Smuzhiyun #define TEGRA210_CLK_CCLK_G 294 329*4882a593Smuzhiyun #define TEGRA210_CLK_CCLK_LP 295 330*4882a593Smuzhiyun #define TEGRA210_CLK_DFLL_REF 296 331*4882a593Smuzhiyun #define TEGRA210_CLK_DFLL_SOC 297 332*4882a593Smuzhiyun #define TEGRA210_CLK_VI_SENSOR2 298 333*4882a593Smuzhiyun #define TEGRA210_CLK_PLL_P_OUT5 299 334*4882a593Smuzhiyun #define TEGRA210_CLK_CML0 300 335*4882a593Smuzhiyun #define TEGRA210_CLK_CML1 301 336*4882a593Smuzhiyun #define TEGRA210_CLK_PLL_C4 302 337*4882a593Smuzhiyun #define TEGRA210_CLK_PLL_DP 303 338*4882a593Smuzhiyun #define TEGRA210_CLK_PLL_E_MUX 304 339*4882a593Smuzhiyun #define TEGRA210_CLK_PLL_MB 305 340*4882a593Smuzhiyun #define TEGRA210_CLK_PLL_A1 306 341*4882a593Smuzhiyun #define TEGRA210_CLK_PLL_D_DSI_OUT 307 342*4882a593Smuzhiyun #define TEGRA210_CLK_PLL_C4_OUT0 308 343*4882a593Smuzhiyun #define TEGRA210_CLK_PLL_C4_OUT1 309 344*4882a593Smuzhiyun #define TEGRA210_CLK_PLL_C4_OUT2 310 345*4882a593Smuzhiyun #define TEGRA210_CLK_PLL_C4_OUT3 311 346*4882a593Smuzhiyun #define TEGRA210_CLK_PLL_U_OUT 312 347*4882a593Smuzhiyun #define TEGRA210_CLK_PLL_U_OUT1 313 348*4882a593Smuzhiyun #define TEGRA210_CLK_PLL_U_OUT2 314 349*4882a593Smuzhiyun #define TEGRA210_CLK_USB2_HSIC_TRK 315 350*4882a593Smuzhiyun #define TEGRA210_CLK_PLL_P_OUT_HSIO 316 351*4882a593Smuzhiyun #define TEGRA210_CLK_PLL_P_OUT_XUSB 317 352*4882a593Smuzhiyun #define TEGRA210_CLK_XUSB_SSP_SRC 318 353*4882a593Smuzhiyun #define TEGRA210_CLK_PLL_RE_OUT1 319 354*4882a593Smuzhiyun #define TEGRA210_CLK_PLL_MB_UD 320 355*4882a593Smuzhiyun #define TEGRA210_CLK_PLL_P_UD 321 356*4882a593Smuzhiyun #define TEGRA210_CLK_ISP 322 357*4882a593Smuzhiyun #define TEGRA210_CLK_PLL_A_OUT_ADSP 323 358*4882a593Smuzhiyun #define TEGRA210_CLK_PLL_A_OUT0_OUT_ADSP 324 359*4882a593Smuzhiyun /* 325 */ 360*4882a593Smuzhiyun #define TEGRA210_CLK_OSC 326 361*4882a593Smuzhiyun #define TEGRA210_CLK_CSI_TPG 327 362*4882a593Smuzhiyun /* 328 */ 363*4882a593Smuzhiyun /* 329 */ 364*4882a593Smuzhiyun /* 330 */ 365*4882a593Smuzhiyun /* 331 */ 366*4882a593Smuzhiyun /* 332 */ 367*4882a593Smuzhiyun /* 333 */ 368*4882a593Smuzhiyun /* 334 */ 369*4882a593Smuzhiyun /* 335 */ 370*4882a593Smuzhiyun /* 336 */ 371*4882a593Smuzhiyun /* 337 */ 372*4882a593Smuzhiyun /* 338 */ 373*4882a593Smuzhiyun /* 339 */ 374*4882a593Smuzhiyun /* 340 */ 375*4882a593Smuzhiyun /* 341 */ 376*4882a593Smuzhiyun /* 342 */ 377*4882a593Smuzhiyun /* 343 */ 378*4882a593Smuzhiyun /* 344 */ 379*4882a593Smuzhiyun /* 345 */ 380*4882a593Smuzhiyun /* 346 */ 381*4882a593Smuzhiyun /* 347 */ 382*4882a593Smuzhiyun /* 348 */ 383*4882a593Smuzhiyun /* 349 */ 384*4882a593Smuzhiyun 385*4882a593Smuzhiyun #define TEGRA210_CLK_AUDIO0_MUX 350 386*4882a593Smuzhiyun #define TEGRA210_CLK_AUDIO1_MUX 351 387*4882a593Smuzhiyun #define TEGRA210_CLK_AUDIO2_MUX 352 388*4882a593Smuzhiyun #define TEGRA210_CLK_AUDIO3_MUX 353 389*4882a593Smuzhiyun #define TEGRA210_CLK_AUDIO4_MUX 354 390*4882a593Smuzhiyun #define TEGRA210_CLK_SPDIF_MUX 355 391*4882a593Smuzhiyun /* 356 */ 392*4882a593Smuzhiyun /* 357 */ 393*4882a593Smuzhiyun /* 358 */ 394*4882a593Smuzhiyun #define TEGRA210_CLK_DSIA_MUX 359 395*4882a593Smuzhiyun #define TEGRA210_CLK_DSIB_MUX 360 396*4882a593Smuzhiyun /* 361 */ 397*4882a593Smuzhiyun #define TEGRA210_CLK_XUSB_SS_DIV2 362 398*4882a593Smuzhiyun 399*4882a593Smuzhiyun #define TEGRA210_CLK_PLL_M_UD 363 400*4882a593Smuzhiyun #define TEGRA210_CLK_PLL_C_UD 364 401*4882a593Smuzhiyun #define TEGRA210_CLK_SCLK_MUX 365 402*4882a593Smuzhiyun 403*4882a593Smuzhiyun #define TEGRA210_CLK_ACLK 370 404*4882a593Smuzhiyun 405*4882a593Smuzhiyun #define TEGRA210_CLK_DMIC1_SYNC_CLK 388 406*4882a593Smuzhiyun #define TEGRA210_CLK_DMIC1_SYNC_CLK_MUX 389 407*4882a593Smuzhiyun #define TEGRA210_CLK_DMIC2_SYNC_CLK 390 408*4882a593Smuzhiyun #define TEGRA210_CLK_DMIC2_SYNC_CLK_MUX 391 409*4882a593Smuzhiyun #define TEGRA210_CLK_DMIC3_SYNC_CLK 392 410*4882a593Smuzhiyun #define TEGRA210_CLK_DMIC3_SYNC_CLK_MUX 393 411*4882a593Smuzhiyun 412*4882a593Smuzhiyun #define TEGRA210_CLK_CLK_MAX 394 413*4882a593Smuzhiyun 414*4882a593Smuzhiyun #endif /* _DT_BINDINGS_CLOCK_TEGRA210_CAR_H */ 415