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Searched refs:RK3568_VP1_DSP_CTRL (Results 1 – 3 of 3) sorted by relevance

/OK3568_Linux_fs/kernel/drivers/gpu/drm/rockchip/
H A Drockchip_vop2_reg.c856 .out_mode = VOP_REG(RK3568_VP1_DSP_CTRL, 0xf, 0),
857 .core_dclk_div = VOP_REG(RK3568_VP1_DSP_CTRL, 0x1, 4),
858 .p2i_en = VOP_REG(RK3568_VP1_DSP_CTRL, 0x1, 5),
859 .dsp_filed_pol = VOP_REG(RK3568_VP1_DSP_CTRL, 0x1, 6),
860 .dsp_interlace = VOP_REG(RK3568_VP1_DSP_CTRL, 0x1, 7),
861 .dsp_data_swap = VOP_REG(RK3568_VP1_DSP_CTRL, 0x1f, 8),
862 .dsp_x_mir_en = VOP_REG(RK3568_VP1_DSP_CTRL, 0x1, 13),
863 .post_dsp_out_r2y = VOP_REG(RK3568_VP1_DSP_CTRL, 0x1, 15),
864 .pre_dither_down_en = VOP_REG(RK3568_VP1_DSP_CTRL, 0x1, 16),
865 .dither_down_en = VOP_REG(RK3568_VP1_DSP_CTRL, 0x1, 17),
[all …]
H A Drockchip_vop_reg.h1152 #define RK3568_VP1_DSP_CTRL 0xD00 macro
/OK3568_Linux_fs/u-boot/drivers/video/drm/
H A Drockchip_vop2.c458 #define RK3568_VP1_DSP_CTRL 0xD00 macro
4830 { RK3528_OVL_PORT1_CTRL, "OVL_VP1", RK3568_VP1_DSP_CTRL, 0x1, 31, 0 },
4832 { RK3568_VP1_DSP_CTRL, "VP1", RK3568_VP1_DSP_CTRL, 0x1, 31, 0 },
5048 { RK3528_OVL_PORT1_CTRL, "OVL_VP1", RK3568_VP1_DSP_CTRL, 0x1, 31, 0 },
5050 { RK3568_VP1_DSP_CTRL, "VP1", RK3568_VP1_DSP_CTRL, 0x1, 31, 0 },
5217 { RK3568_VP0_DSP_CTRL, "VP0", RK3568_VP1_DSP_CTRL, 0x1, 31, 0 },
5218 { RK3568_VP1_DSP_CTRL, "VP1", RK3568_VP1_DSP_CTRL, 0x1, 31, 0 },
5460 { RK3568_VP1_DSP_CTRL, "VP1", RK3568_VP1_DSP_CTRL, 0x1, 31, 0 },