Searched refs:RGA2_MASK_BASE_OFFSET (Results 1 – 4 of 4) sorted by relevance
189 bRGA_MASK_ADDR = (RK_U32 *)(base + RGA2_MASK_BASE_OFFSET); in RGA2_set_reg_src_info()784 bRGA_MASK_ADDR = (RK_U32 *)(base + RGA2_MASK_BASE_OFFSET); in RGA2_set_reg_rop_info()938 bRGA_MASK_ADDR = (RK_U32 *)(base + RGA2_MASK_BASE_OFFSET); in RGA2_set_reg_color_fill()970 bRGA_MASK_BASE = (RK_U32 *)(base + RGA2_MASK_BASE_OFFSET); in RGA2_set_reg_update_palette_table()996 bRGA_PAT_MST = (RK_U32 *)(base + RGA2_MASK_BASE_OFFSET); in RGA2_set_reg_update_patten_buff()
317 #define RGA2_MASK_BASE_OFFSET 0x68 macro
88 #define RGA2_MASK_BASE_OFFSET 0x068 macro
241 bRGA_MASK_ADDR = (u32 *) (base + RGA2_MASK_BASE_OFFSET); in RGA2_set_reg_src_info()1549 bRGA_MASK_ADDR = (u32 *) (base + RGA2_MASK_BASE_OFFSET); in RGA2_set_reg_rop_info()1748 bRGA_MASK_ADDR = (u32 *) (base + RGA2_MASK_BASE_OFFSET); in RGA2_set_reg_color_fill()1783 bRGA_MASK_BASE = (u32 *) (base + RGA2_MASK_BASE_OFFSET); in RGA2_set_reg_update_palette_table()1808 bRGA_PAT_MST = (u32 *) (base + RGA2_MASK_BASE_OFFSET); in RGA2_set_reg_update_patten_buff()