Searched refs:REG_SET_0x68_0_8_H_DLY_LSB (Results 1 – 2 of 2) sorted by relevance
91 #define REG_SET_0x68_0_8_H_DLY_LSB(ch, val) vd_register_set ( 0 , 0x00 , 0x68 + ch , val , 0 , 8 ) macro
348 REG_SET_0x68_0_8_H_DLY_LSB( ch, param->h_delay_lsb ); in vd_vi_h_timing_set_seq5()