Searched refs:PCIE2_BAR0_CORE2_WIN2 (Results 1 – 13 of 13) sorted by relevance
240 #define PCIE2_BAR0_CORE2_WIN2 0x78 /* backplane addres space accessed by second 4KB of BAR0 */ macro
311 #define PCIE2_BAR0_CORE2_WIN2 0x78 /* backplane addres space accessed by second 4KB of BAR0 */ macro
631 #define PCIE2_BAR0_CORE2_WIN2 0x78 /* config register to map 6th 4KB of BAR0 */ macro
1198 cfg_reg = PCIE2_BAR0_CORE2_WIN2; in ai_dumpregs()1322 cfg_reg = PCIE2_BAR0_CORE2_WIN2; in ai_enable_backplane_timeouts()1734 cfg_reg = PCIE2_BAR0_CORE2_WIN2; in ai_clear_backplane_to()
598 OSL_PCI_WRITE_CONFIG(sii->osh, PCIE2_BAR0_CORE2_WIN2, 4, wrap); in BCMPOSTTRAPFN()1444 cfg_reg = PCIE2_BAR0_CORE2_WIN2; in ai_dumpregs()1675 cfg_reg = PCIE2_BAR0_CORE2_WIN2; in ai_update_backplane_timeouts()2270 cfg_reg = PCIE2_BAR0_CORE2_WIN2; in BCMPOSTTRAPFN()
1422 OSL_PCI_WRITE_CONFIG(sii->osh, PCIE2_BAR0_CORE2_WIN2, PCIE_WRITE_SIZE, curwrap); in _nci_setcoreidx_pcie_bus()
1361 cfg_reg = PCIE2_BAR0_CORE2_WIN2; in ai_dumpregs()1478 cfg_reg = PCIE2_BAR0_CORE2_WIN2; in ai_update_backplane_timeouts()1962 cfg_reg = PCIE2_BAR0_CORE2_WIN2; in ai_clear_backplane_to()