1 /* 2 * pcicfg.h: PCI configuration constants and structures. 3 * 4 * Portions of this code are copyright (c) 2021 Cypress Semiconductor Corporation 5 * 6 * Copyright (C) 1999-2017, Broadcom Corporation 7 * 8 * Unless you and Broadcom execute a separate written software license 9 * agreement governing use of this software, this software is licensed to you 10 * under the terms of the GNU General Public License version 2 (the "GPL"), 11 * available at http://www.broadcom.com/licenses/GPLv2.php, with the 12 * following added to such license: 13 * 14 * As a special exception, the copyright holders of this software give you 15 * permission to link this software with independent modules, and to copy and 16 * distribute the resulting executable under terms of your choice, provided that 17 * you also meet, for each linked independent module, the terms and conditions of 18 * the license of that module. An independent module is a module which is not 19 * derived from this software. The special exception does not apply to any 20 * modifications of the software. 21 * 22 * Notwithstanding the above, under no circumstances may you combine this 23 * software in any way with any other Broadcom software provided under a license 24 * other than the GPL, without Broadcom's express prior written consent. 25 * 26 * 27 * <<Broadcom-WL-IPTag/Open:>> 28 * 29 * $Id: pcicfg.h 690133 2017-03-14 21:02:02Z $ 30 */ 31 32 #ifndef _h_pcicfg_ 33 #define _h_pcicfg_ 34 35 /* pci config status reg has a bit to indicate that capability ptr is present */ 36 37 #define PCI_CAPPTR_PRESENT 0x0010 38 39 /* A structure for the config registers is nice, but in most 40 * systems the config space is not memory mapped, so we need 41 * field offsetts. :-( 42 */ 43 #define PCI_CFG_VID 0 44 #define PCI_CFG_DID 2 45 #define PCI_CFG_CMD 4 46 #define PCI_CFG_STAT 6 47 #define PCI_CFG_REV 8 48 #define PCI_CFG_PROGIF 9 49 #define PCI_CFG_SUBCL 0xa 50 #define PCI_CFG_BASECL 0xb 51 #define PCI_CFG_CLSZ 0xc 52 #define PCI_CFG_LATTIM 0xd 53 #define PCI_CFG_HDR 0xe 54 #define PCI_CFG_BIST 0xf 55 #define PCI_CFG_BAR0 0x10 56 /* 57 * TODO: PCI_CFG_BAR1 is wrongly defined to be 0x14 whereas it should be 58 * 0x18 as per the PCIe full dongle spec. Need to modify the values below 59 * correctly at a later point of time 60 */ 61 #define PCI_CFG_BAR1 0x14 62 #define PCI_CFG_BAR2 0x18 63 #define PCI_CFG_BAR3 0x1c 64 #define PCI_CFG_BAR4 0x20 65 #define PCI_CFG_BAR5 0x24 66 #define PCI_CFG_CIS 0x28 67 #define PCI_CFG_SVID 0x2c 68 #define PCI_CFG_SSID 0x2e 69 #define PCI_CFG_ROMBAR 0x30 70 #define PCI_CFG_CAPPTR 0x34 71 #define PCI_CFG_INT 0x3c 72 #define PCI_CFG_PIN 0x3d 73 #define PCI_CFG_MINGNT 0x3e 74 #define PCI_CFG_MAXLAT 0x3f 75 #define PCI_CFG_DEVCTRL 0xd8 76 #define PCI_CFG_TLCNTRL_5 0x814 77 78 /* PCI CAPABILITY DEFINES */ 79 #define PCI_CAP_POWERMGMTCAP_ID 0x01 80 #define PCI_CAP_MSICAP_ID 0x05 81 #define PCI_CAP_VENDSPEC_ID 0x09 82 #define PCI_CAP_PCIECAP_ID 0x10 83 #define PCI_CAP_MSIXCAP_ID 0x11 84 85 /* Data structure to define the Message Signalled Interrupt facility 86 * Valid for PCI and PCIE configurations 87 */ 88 typedef struct _pciconfig_cap_msi { 89 uint8 capID; 90 uint8 nextptr; 91 uint16 msgctrl; 92 uint32 msgaddr; 93 } pciconfig_cap_msi; 94 #define MSI_ENABLE 0x1 /* bit 0 of msgctrl */ 95 96 /* Data structure to define the Power managment facility 97 * Valid for PCI and PCIE configurations 98 */ 99 typedef struct _pciconfig_cap_pwrmgmt { 100 uint8 capID; 101 uint8 nextptr; 102 uint16 pme_cap; 103 uint16 pme_sts_ctrl; 104 uint8 pme_bridge_ext; 105 uint8 data; 106 } pciconfig_cap_pwrmgmt; 107 108 #define PME_CAP_PM_STATES (0x1f << 27) /* Bits 31:27 states that can generate PME */ 109 #define PME_CSR_OFFSET 0x4 /* 4-bytes offset */ 110 #define PME_CSR_PME_EN (1 << 8) /* Bit 8 Enable generating of PME */ 111 #define PME_CSR_PME_STAT (1 << 15) /* Bit 15 PME got asserted */ 112 113 /* Data structure to define the PCIE capability */ 114 typedef struct _pciconfig_cap_pcie { 115 uint8 capID; 116 uint8 nextptr; 117 uint16 pcie_cap; 118 uint32 dev_cap; 119 uint16 dev_ctrl; 120 uint16 dev_status; 121 uint32 link_cap; 122 uint16 link_ctrl; 123 uint16 link_status; 124 uint32 slot_cap; 125 uint16 slot_ctrl; 126 uint16 slot_status; 127 uint16 root_ctrl; 128 uint16 root_cap; 129 uint32 root_status; 130 } pciconfig_cap_pcie; 131 132 /* PCIE Enhanced CAPABILITY DEFINES */ 133 #define PCIE_EXTCFG_OFFSET 0x100 134 #define PCIE_ADVERRREP_CAPID 0x0001 135 #define PCIE_VC_CAPID 0x0002 136 #define PCIE_DEVSNUM_CAPID 0x0003 137 #define PCIE_PWRBUDGET_CAPID 0x0004 138 139 /* PCIE Extended configuration */ 140 #define PCIE_ADV_CORR_ERR_MASK 0x114 141 #define PCIE_ADV_CORR_ERR_MASK_OFFSET 0x14 142 #define CORR_ERR_RE (1 << 0) /* Receiver */ 143 #define CORR_ERR_BT (1 << 6) /* Bad TLP */ 144 #define CORR_ERR_BD (1 << 7) /* Bad DLLP */ 145 #define CORR_ERR_RR (1 << 8) /* REPLAY_NUM rollover */ 146 #define CORR_ERR_RT (1 << 12) /* Reply timer timeout */ 147 #define CORR_ERR_AE (1 << 13) /* Adviosry Non-Fital Error Mask */ 148 #define ALL_CORR_ERRORS (CORR_ERR_RE | CORR_ERR_BT | CORR_ERR_BD | \ 149 CORR_ERR_RR | CORR_ERR_RT) 150 151 /* PCIE Root Control Register bits (Host mode only) */ 152 #define PCIE_RC_CORR_SERR_EN 0x0001 153 #define PCIE_RC_NONFATAL_SERR_EN 0x0002 154 #define PCIE_RC_FATAL_SERR_EN 0x0004 155 #define PCIE_RC_PME_INT_EN 0x0008 156 #define PCIE_RC_CRS_EN 0x0010 157 158 /* PCIE Root Capability Register bits (Host mode only) */ 159 #define PCIE_RC_CRS_VISIBILITY 0x0001 160 161 /* PCIe PMCSR Register bits */ 162 #define PCIE_PMCSR_PMESTAT 0x8000 163 164 /* Header to define the PCIE specific capabilities in the extended config space */ 165 typedef struct _pcie_enhanced_caphdr { 166 uint16 capID; 167 uint16 cap_ver : 4; 168 uint16 next_ptr : 12; 169 } pcie_enhanced_caphdr; 170 171 #define PCIE_CFG_PMCSR 0x4C 172 #define PCI_BAR0_WIN 0x80 /* backplane addres space accessed by BAR0 */ 173 #define PCI_BAR1_WIN 0x84 /* backplane addres space accessed by BAR1 */ 174 #define PCI_SPROM_CONTROL 0x88 /* sprom property control */ 175 #define PCIE_CFG_SUBSYSTEM_CONTROL 0x88 /* used as subsystem control in PCIE devices */ 176 #define PCI_BAR1_CONTROL 0x8c /* BAR1 region burst control */ 177 #define PCI_INT_STATUS 0x90 /* PCI and other cores interrupts */ 178 #define PCI_INT_MASK 0x94 /* mask of PCI and other cores interrupts */ 179 #define PCI_TO_SB_MB 0x98 /* signal backplane interrupts */ 180 #define PCI_BACKPLANE_ADDR 0xa0 /* address an arbitrary location on the system backplane */ 181 #define PCI_BACKPLANE_DATA 0xa4 /* data at the location specified by above address */ 182 #define PCI_CLK_CTL_ST 0xa8 /* pci config space clock control/status (>=rev14) */ 183 #define PCI_BAR0_WIN2 0xac /* backplane addres space accessed by second 4KB of BAR0 */ 184 #define PCI_GPIO_IN 0xb0 /* pci config space gpio input (>=rev3) */ 185 #define PCIE_CFG_DEVICE_CAPABILITY 0xb0 /* used as device capability in PCIE devices */ 186 #define PCI_GPIO_OUT 0xb4 /* pci config space gpio output (>=rev3) */ 187 #define PCIE_CFG_DEVICE_CONTROL 0xb4 /* 0xb4 is used as device control in PCIE devices */ 188 #define PCIE_DC_AER_CORR_EN (1u << 0u) 189 #define PCIE_DC_AER_NON_FATAL_EN (1u << 1u) 190 #define PCIE_DC_AER_FATAL_EN (1u << 2u) 191 #define PCIE_DC_AER_UNSUP_EN (1u << 3u) 192 193 #define PCI_BAR0_WIN2_OFFSET 0x1000u 194 #define PCIE2_BAR0_CORE2_WIN2_OFFSET 0x5000u 195 196 #define PCI_GPIO_OUTEN 0xb8 /* pci config space gpio output enable (>=rev3) */ 197 #define PCI_PM_L1SS_CTRL2 0x24c /* The L1 PM Substates Control register */ 198 199 /* Private Registers */ 200 #define PCI_STAT_CTRL 0xa80 201 #define PCI_L0_EVENTCNT 0xa84 202 #define PCI_L0_STATETMR 0xa88 203 #define PCI_L1_EVENTCNT 0xa8c 204 #define PCI_L1_STATETMR 0xa90 205 #define PCI_L1_1_EVENTCNT 0xa94 206 #define PCI_L1_1_STATETMR 0xa98 207 #define PCI_L1_2_EVENTCNT 0xa9c 208 #define PCI_L1_2_STATETMR 0xaa0 209 #define PCI_L2_EVENTCNT 0xaa4 210 #define PCI_L2_STATETMR 0xaa8 211 212 #define PCI_LINK_STATUS 0x4dc 213 #define PCI_LINK_SPEED_MASK (15u << 0u) 214 #define PCI_LINK_SPEED_SHIFT (0) 215 #define PCIE_LNK_SPEED_GEN1 0x1 216 #define PCIE_LNK_SPEED_GEN2 0x2 217 #define PCIE_LNK_SPEED_GEN3 0x3 218 219 #define PCI_PL_SPARE 0x1808 /* Config to Increase external clkreq deasserted minimum time */ 220 #define PCI_CONFIG_EXT_CLK_MIN_TIME_MASK (1u << 31u) 221 #define PCI_CONFIG_EXT_CLK_MIN_TIME_SHIFT (31) 222 223 #define PCI_ADV_ERR_CAP 0x100 224 #define PCI_UC_ERR_STATUS 0x104 225 #define PCI_UNCORR_ERR_MASK 0x108 226 #define PCI_UCORR_ERR_SEVR 0x10c 227 #define PCI_CORR_ERR_STATUS 0x110 228 #define PCI_CORR_ERR_MASK 0x114 229 #define PCI_ERR_CAP_CTRL 0x118 230 #define PCI_TLP_HDR_LOG1 0x11c 231 #define PCI_TLP_HDR_LOG2 0x120 232 #define PCI_TLP_HDR_LOG3 0x124 233 #define PCI_TLP_HDR_LOG4 0x128 234 #define PCI_TL_CTRL_5 0x814 235 #define PCI_TL_HDR_FC_ST 0x980 236 #define PCI_TL_TGT_CRDT_ST 0x990 237 #define PCI_TL_SMLOGIC_ST 0x998 238 #define PCI_DL_ATTN_VEC 0x1040 239 #define PCI_DL_STATUS 0x1048 240 241 #define PCI_PHY_CTL_0 0x1800 242 #define PCI_SLOW_PMCLK_EXT_RLOCK (1 << 7) 243 244 #define PCI_LINK_STATE_DEBUG 0x1c24 245 #define PCI_RECOVERY_HIST 0x1ce4 246 #define PCI_PHY_LTSSM_HIST_0 0x1cec 247 #define PCI_PHY_LTSSM_HIST_1 0x1cf0 248 #define PCI_PHY_LTSSM_HIST_2 0x1cf4 249 #define PCI_PHY_LTSSM_HIST_3 0x1cf8 250 #define PCI_PHY_DBG_CLKREG_0 0x1e10 251 #define PCI_PHY_DBG_CLKREG_1 0x1e14 252 #define PCI_PHY_DBG_CLKREG_2 0x1e18 253 #define PCI_PHY_DBG_CLKREG_3 0x1e1c 254 255 /* Bit settings for PCIE_CFG_SUBSYSTEM_CONTROL register */ 256 #define PCIE_BAR1COHERENTACCEN_BIT 8 257 #define PCIE_BAR2COHERENTACCEN_BIT 9 258 #define PCIE_SSRESET_STATUS_BIT 13 259 #define PCIE_SSRESET_DISABLE_BIT 14 260 #define PCIE_SSRESET_DIS_ENUM_RST_BIT 15 261 262 #define PCIE_BARCOHERENTACCEN_MASK 0x300 263 264 /* Bit settings for PCI_UC_ERR_STATUS register */ 265 #define PCI_UC_ERR_URES (1 << 20) /* Unsupported Request Error Status */ 266 #define PCI_UC_ERR_ECRCS (1 << 19) /* ECRC Error Status */ 267 #define PCI_UC_ERR_MTLPS (1 << 18) /* Malformed TLP Status */ 268 #define PCI_UC_ERR_ROS (1 << 17) /* Receiver Overflow Status */ 269 #define PCI_UC_ERR_UCS (1 << 16) /* Unexpected Completion Status */ 270 #define PCI_UC_ERR_CAS (1 << 15) /* Completer Abort Status */ 271 #define PCI_UC_ERR_CTS (1 << 14) /* Completer Timeout Status */ 272 #define PCI_UC_ERR_FCPES (1 << 13) /* Flow Control Protocol Error Status */ 273 #define PCI_UC_ERR_PTLPS (1 << 12) /* Poisoned TLP Status */ 274 #define PCI_UC_ERR_DLPES (1 << 4) /* Data Link Protocol Error Status */ 275 276 #define PCI_DL_STATUS_PHY_LINKUP (1 << 13) /* Status of LINK */ 277 278 #define PCI_PMCR_REFUP 0x1814 /* Trefup time */ 279 #define PCI_PMCR_TREFUP_LO_MASK 0x3f 280 #define PCI_PMCR_TREFUP_LO_SHIFT 24 281 #define PCI_PMCR_TREFUP_LO_BITS 6 282 #define PCI_PMCR_TREFUP_HI_MASK 0xf 283 #define PCI_PMCR_TREFUP_HI_SHIFT 5 284 #define PCI_PMCR_TREFUP_HI_BITS 4 285 #define PCI_PMCR_TREFUP_MAX 0x400 286 #define PCI_PMCR_TREFUP_MAX_SCALE 0x2000 287 288 #define PCI_PMCR_REFUP_EXT 0x1818 /* Trefup extend Max */ 289 #define PCI_PMCR_TREFUP_EXT_SHIFT 22 290 #define PCI_PMCR_TREFUP_EXT_SCALE 3 291 #define PCI_PMCR_TREFUP_EXT_ON 1 292 #define PCI_PMCR_TREFUP_EXT_OFF 0 293 294 #define PCI_TPOWER_SCALE_MASK 0x3 295 #define PCI_TPOWER_SCALE_SHIFT 3 /* 0:1 is scale and 2 is rsvd */ 296 297 #define PCI_BAR0_SHADOW_OFFSET (2 * 1024) /* bar0 + 2K accesses sprom shadow (in pci core) */ 298 #define PCI_BAR0_SPROM_OFFSET (4 * 1024) /* bar0 + 4K accesses external sprom */ 299 #define PCI_BAR0_PCIREGS_OFFSET (6 * 1024) /* bar0 + 6K accesses pci core registers */ 300 #define PCI_BAR0_PCISBR_OFFSET (4 * 1024) /* pci core SB registers are at the end of the 301 * 8KB window, so their address is the "regular" 302 * address plus 4K 303 */ 304 /* 305 * PCIE GEN2 changed some of the above locations for 306 * Bar0WrapperBase, SecondaryBAR0Window and SecondaryBAR0WrapperBase 307 * BAR0 maps 32K of register space 308 */ 309 #define PCIE2_BAR0_WIN2 0x70 /* backplane addres space accessed by second 4KB of BAR0 */ 310 #define PCIE2_BAR0_CORE2_WIN 0x74 /* backplane addres space accessed by second 4KB of BAR0 */ 311 #define PCIE2_BAR0_CORE2_WIN2 0x78 /* backplane addres space accessed by second 4KB of BAR0 */ 312 #define PCIE2_BAR0_WINSZ 0x8000 313 314 #define PCI_BAR0_WIN2_OFFSET 0x1000u 315 #define PCI_CORE_ENUM_OFFSET 0x2000u 316 #define PCI_CC_CORE_ENUM_OFFSET 0x3000u 317 #define PCI_SEC_BAR0_WIN_OFFSET 0x4000u 318 #define PCI_SEC_BAR0_WRAP_OFFSET 0x5000u 319 #define PCI_CORE_ENUM2_OFFSET 0x6000u 320 #define PCI_CC_CORE_ENUM2_OFFSET 0x7000u 321 #define PCI_LAST_OFFSET 0x8000u 322 323 #define PCI_BAR0_WINSZ (16 * 1024) /* bar0 window size Match with corerev 13 */ 324 /* On pci corerev >= 13 and all pcie, the bar0 is now 16KB and it maps: */ 325 #define PCI_16KB0_PCIREGS_OFFSET (8 * 1024) /* bar0 + 8K accesses pci/pcie core registers */ 326 #define PCI_16KB0_CCREGS_OFFSET (12 * 1024) /* bar0 + 12K accesses chipc core registers */ 327 #define PCI_16KBB0_WINSZ (16 * 1024) /* bar0 window size */ 328 #define PCI_SECOND_BAR0_OFFSET (16 * 1024) /* secondary bar 0 window */ 329 330 /* On AI chips we have a second window to map DMP regs are mapped: */ 331 #define PCI_16KB0_WIN2_OFFSET (4 * 1024) /* bar0 + 4K is "Window 2" */ 332 333 /* PCI_INT_STATUS */ 334 #define PCI_SBIM_STATUS_SERR 0x4 /* backplane SBErr interrupt status */ 335 336 /* PCI_INT_MASK */ 337 #define PCI_SBIM_SHIFT 8 /* backplane core interrupt mask bits offset */ 338 #define PCI_SBIM_MASK 0xff00 /* backplane core interrupt mask */ 339 #define PCI_SBIM_MASK_SERR 0x4 /* backplane SBErr interrupt mask */ 340 #define PCI_CTO_INT_SHIFT 16 /* backplane SBErr interrupt mask */ 341 #define PCI_CTO_INT_MASK (1 << PCI_CTO_INT_SHIFT) /* backplane SBErr interrupt mask */ 342 343 /* PCI_SPROM_CONTROL */ 344 #define SPROM_SZ_MSK 0x02 /* SPROM Size Mask */ 345 #define SPROM_LOCKED 0x08 /* SPROM Locked */ 346 #define SPROM_BLANK 0x04 /* indicating a blank SPROM */ 347 #define SPROM_WRITEEN 0x10 /* SPROM write enable */ 348 #define SPROM_BOOTROM_WE 0x20 /* external bootrom write enable */ 349 #define SPROM_BACKPLANE_EN 0x40 /* Enable indirect backplane access */ 350 #define SPROM_OTPIN_USE 0x80 /* device OTP In use */ 351 #define SPROM_CFG_TO_SB_RST 0x400 /* backplane reset */ 352 353 /* Bits in PCI command and status regs */ 354 #define PCI_CMD_IO 0x00000001 /* I/O enable */ 355 #define PCI_CMD_MEMORY 0x00000002 /* Memory enable */ 356 #define PCI_CMD_MASTER 0x00000004 /* Master enable */ 357 #define PCI_CMD_SPECIAL 0x00000008 /* Special cycles enable */ 358 #define PCI_CMD_INVALIDATE 0x00000010 /* Invalidate? */ 359 #define PCI_CMD_VGA_PAL 0x00000040 /* VGA Palate */ 360 #define PCI_STAT_TA 0x08000000 /* target abort status */ 361 362 /* Header types */ 363 #define PCI_HEADER_MULTI 0x80 364 #define PCI_HEADER_MASK 0x7f 365 typedef enum { 366 PCI_HEADER_NORMAL, 367 PCI_HEADER_BRIDGE, 368 PCI_HEADER_CARDBUS 369 } pci_header_types; 370 371 #define PCI_CONFIG_SPACE_SIZE 256 372 373 #define DWORD_ALIGN(x) (x & ~(0x03)) 374 #define BYTE_POS(x) (x & 0x3) 375 #define WORD_POS(x) (x & 0x1) 376 377 #define BYTE_SHIFT(x) (8 * BYTE_POS(x)) 378 #define WORD_SHIFT(x) (16 * WORD_POS(x)) 379 380 #define BYTE_VAL(a, x) ((a >> BYTE_SHIFT(x)) & 0xFF) 381 #define WORD_VAL(a, x) ((a >> WORD_SHIFT(x)) & 0xFFFF) 382 383 #define read_pci_cfg_byte(a) \ 384 (BYTE_VAL(OSL_PCI_READ_CONFIG(osh, DWORD_ALIGN(a), 4), a) & 0xff) 385 386 #define read_pci_cfg_word(a) \ 387 (WORD_VAL(OSL_PCI_READ_CONFIG(osh, DWORD_ALIGN(a), 4), a) & 0xffff) 388 389 #define write_pci_cfg_byte(a, val) do { \ 390 uint32 tmpval; \ 391 tmpval = (OSL_PCI_READ_CONFIG(osh, DWORD_ALIGN(a), 4) & ~0xFF << BYTE_POS(a)) | \ 392 val << BYTE_POS(a); \ 393 OSL_PCI_WRITE_CONFIG(osh, DWORD_ALIGN(a), 4, tmpval); \ 394 } while (0) 395 396 #define write_pci_cfg_word(a, val) do { \ 397 uint32 tmpval; \ 398 tmpval = (OSL_PCI_READ_CONFIG(osh, DWORD_ALIGN(a), 4) & ~0xFFFF << WORD_POS(a)) | \ 399 val << WORD_POS(a); \ 400 OSL_PCI_WRITE_CONFIG(osh, DWORD_ALIGN(a), 4, tmpval); \ 401 } while (0) 402 403 #endif /* _h_pcicfg_ */ 404