Searched refs:OPER_WRITE (Results 1 – 5 of 5) sorted by relevance
56 tx_burst_size = (direction == OPER_WRITE) ? in ddr3_tip_bist_activate()58 delay_between_burst = (direction == OPER_WRITE) ? 2 : 0; in ddr3_tip_bist_activate()59 rd_mode = (direction == OPER_WRITE) ? 1 : 0; in ddr3_tip_bist_activate()198 i, OPER_WRITE, STRESS_NONE, in hws_ddr3_run_bist()
238 tx_burst_size = (direction == OPER_WRITE) ? in ddr3_tip_ip_training()240 delay_between_burst = (direction == OPER_WRITE) ? 2 : 0; in ddr3_tip_ip_training()241 rd_mode = (direction == OPER_WRITE) ? 1 : 0; in ddr3_tip_ip_training()301 direction == OPER_WRITE) { in ddr3_tip_ip_training()305 direction == OPER_WRITE) { in ddr3_tip_ip_training()320 direction == OPER_WRITE) { in ddr3_tip_ip_training()906 u8 cons_tap = (direction == OPER_WRITE) ? (64) : (0); in ddr3_tip_ip_training_wrapper_int()1007 u8 cons_tap = (direction == OPER_WRITE) ? (64) : (0); in ddr3_tip_ip_training_wrapper()
156 OPER_WRITE, enumerator
99 direction = OPER_WRITE; in ddr3_tip_centralization()395 OPER_WRITE) { in ddr3_tip_centralization()
47 enum hws_dir dir = (pbs_mode == PBS_RX_MODE) ? OPER_READ : OPER_WRITE; in ddr3_tip_pbs()