Searched refs:MXS_DMA_DESC_WAIT4END (Results 1 – 3 of 3) sorted by relevance
313 MXS_DMA_DESC_WAIT4END | (3 << MXS_DMA_DESC_PIO_WORDS_OFFSET) | in mxs_nand_cmd_ctrl()429 MXS_DMA_DESC_DEC_SEM | MXS_DMA_DESC_WAIT4END | in mxs_nand_read_buf()456 MXS_DMA_DESC_WAIT4END | (1 << MXS_DMA_DESC_PIO_WORDS_OFFSET); in mxs_nand_read_buf()515 MXS_DMA_DESC_DEC_SEM | MXS_DMA_DESC_WAIT4END | in mxs_nand_write_buf()570 MXS_DMA_DESC_NAND_WAIT_4_READY | MXS_DMA_DESC_WAIT4END | in mxs_nand_ecc_read_page()587 MXS_DMA_DESC_WAIT4END | (6 << MXS_DMA_DESC_PIO_WORDS_OFFSET); in mxs_nand_ecc_read_page()612 MXS_DMA_DESC_NAND_WAIT_4_READY | MXS_DMA_DESC_WAIT4END | in mxs_nand_ecc_read_page()725 MXS_DMA_DESC_DEC_SEM | MXS_DMA_DESC_WAIT4END | in mxs_nand_ecc_write_page()
90 #define MXS_DMA_DESC_WAIT4END (1 << 7) macro
234 MXS_DMA_DESC_WAIT4END | in video_hw_init()