1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Freescale i.MX28 APBH DMA 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com> 5*4882a593Smuzhiyun * on behalf of DENX Software Engineering GmbH 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * Based on code from LTIB: 8*4882a593Smuzhiyun * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. 9*4882a593Smuzhiyun * 10*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 11*4882a593Smuzhiyun */ 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun #ifndef __DMA_H__ 14*4882a593Smuzhiyun #define __DMA_H__ 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun #include <linux/list.h> 17*4882a593Smuzhiyun #include <linux/compiler.h> 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun #define DMA_PIO_WORDS 15 20*4882a593Smuzhiyun #define MXS_DMA_ALIGNMENT ARCH_DMA_MINALIGN 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun /* 23*4882a593Smuzhiyun * MXS DMA channels 24*4882a593Smuzhiyun */ 25*4882a593Smuzhiyun #if defined(CONFIG_MX23) 26*4882a593Smuzhiyun enum { 27*4882a593Smuzhiyun MXS_DMA_CHANNEL_AHB_APBH_LCDIF = 0, 28*4882a593Smuzhiyun MXS_DMA_CHANNEL_AHB_APBH_SSP0, 29*4882a593Smuzhiyun MXS_DMA_CHANNEL_AHB_APBH_SSP1, 30*4882a593Smuzhiyun MXS_DMA_CHANNEL_AHB_APBH_RESERVED0, 31*4882a593Smuzhiyun MXS_DMA_CHANNEL_AHB_APBH_GPMI0, 32*4882a593Smuzhiyun MXS_DMA_CHANNEL_AHB_APBH_GPMI1, 33*4882a593Smuzhiyun MXS_DMA_CHANNEL_AHB_APBH_GPMI2, 34*4882a593Smuzhiyun MXS_DMA_CHANNEL_AHB_APBH_GPMI3, 35*4882a593Smuzhiyun MXS_MAX_DMA_CHANNELS, 36*4882a593Smuzhiyun }; 37*4882a593Smuzhiyun #elif defined(CONFIG_MX28) 38*4882a593Smuzhiyun enum { 39*4882a593Smuzhiyun MXS_DMA_CHANNEL_AHB_APBH_SSP0 = 0, 40*4882a593Smuzhiyun MXS_DMA_CHANNEL_AHB_APBH_SSP1, 41*4882a593Smuzhiyun MXS_DMA_CHANNEL_AHB_APBH_SSP2, 42*4882a593Smuzhiyun MXS_DMA_CHANNEL_AHB_APBH_SSP3, 43*4882a593Smuzhiyun MXS_DMA_CHANNEL_AHB_APBH_GPMI0, 44*4882a593Smuzhiyun MXS_DMA_CHANNEL_AHB_APBH_GPMI1, 45*4882a593Smuzhiyun MXS_DMA_CHANNEL_AHB_APBH_GPMI2, 46*4882a593Smuzhiyun MXS_DMA_CHANNEL_AHB_APBH_GPMI3, 47*4882a593Smuzhiyun MXS_DMA_CHANNEL_AHB_APBH_GPMI4, 48*4882a593Smuzhiyun MXS_DMA_CHANNEL_AHB_APBH_GPMI5, 49*4882a593Smuzhiyun MXS_DMA_CHANNEL_AHB_APBH_GPMI6, 50*4882a593Smuzhiyun MXS_DMA_CHANNEL_AHB_APBH_GPMI7, 51*4882a593Smuzhiyun MXS_DMA_CHANNEL_AHB_APBH_HSADC, 52*4882a593Smuzhiyun MXS_DMA_CHANNEL_AHB_APBH_LCDIF, 53*4882a593Smuzhiyun MXS_DMA_CHANNEL_AHB_APBH_RESERVED0, 54*4882a593Smuzhiyun MXS_DMA_CHANNEL_AHB_APBH_RESERVED1, 55*4882a593Smuzhiyun MXS_MAX_DMA_CHANNELS, 56*4882a593Smuzhiyun }; 57*4882a593Smuzhiyun #elif defined(CONFIG_MX6) || defined(CONFIG_MX7) 58*4882a593Smuzhiyun enum { 59*4882a593Smuzhiyun MXS_DMA_CHANNEL_AHB_APBH_GPMI0 = 0, 60*4882a593Smuzhiyun MXS_DMA_CHANNEL_AHB_APBH_GPMI1, 61*4882a593Smuzhiyun MXS_DMA_CHANNEL_AHB_APBH_GPMI2, 62*4882a593Smuzhiyun MXS_DMA_CHANNEL_AHB_APBH_GPMI3, 63*4882a593Smuzhiyun MXS_DMA_CHANNEL_AHB_APBH_GPMI4, 64*4882a593Smuzhiyun MXS_DMA_CHANNEL_AHB_APBH_GPMI5, 65*4882a593Smuzhiyun MXS_DMA_CHANNEL_AHB_APBH_GPMI6, 66*4882a593Smuzhiyun MXS_DMA_CHANNEL_AHB_APBH_GPMI7, 67*4882a593Smuzhiyun MXS_MAX_DMA_CHANNELS, 68*4882a593Smuzhiyun }; 69*4882a593Smuzhiyun #endif 70*4882a593Smuzhiyun 71*4882a593Smuzhiyun /* 72*4882a593Smuzhiyun * MXS DMA hardware command. 73*4882a593Smuzhiyun * 74*4882a593Smuzhiyun * This structure describes the in-memory layout of an entire DMA command, 75*4882a593Smuzhiyun * including space for the maximum number of PIO accesses. See the appropriate 76*4882a593Smuzhiyun * reference manual for a detailed description of what these fields mean to the 77*4882a593Smuzhiyun * DMA hardware. 78*4882a593Smuzhiyun */ 79*4882a593Smuzhiyun #define MXS_DMA_DESC_COMMAND_MASK 0x3 80*4882a593Smuzhiyun #define MXS_DMA_DESC_COMMAND_OFFSET 0 81*4882a593Smuzhiyun #define MXS_DMA_DESC_COMMAND_NO_DMAXFER 0x0 82*4882a593Smuzhiyun #define MXS_DMA_DESC_COMMAND_DMA_WRITE 0x1 83*4882a593Smuzhiyun #define MXS_DMA_DESC_COMMAND_DMA_READ 0x2 84*4882a593Smuzhiyun #define MXS_DMA_DESC_COMMAND_DMA_SENSE 0x3 85*4882a593Smuzhiyun #define MXS_DMA_DESC_CHAIN (1 << 2) 86*4882a593Smuzhiyun #define MXS_DMA_DESC_IRQ (1 << 3) 87*4882a593Smuzhiyun #define MXS_DMA_DESC_NAND_LOCK (1 << 4) 88*4882a593Smuzhiyun #define MXS_DMA_DESC_NAND_WAIT_4_READY (1 << 5) 89*4882a593Smuzhiyun #define MXS_DMA_DESC_DEC_SEM (1 << 6) 90*4882a593Smuzhiyun #define MXS_DMA_DESC_WAIT4END (1 << 7) 91*4882a593Smuzhiyun #define MXS_DMA_DESC_HALT_ON_TERMINATE (1 << 8) 92*4882a593Smuzhiyun #define MXS_DMA_DESC_TERMINATE_FLUSH (1 << 9) 93*4882a593Smuzhiyun #define MXS_DMA_DESC_PIO_WORDS_MASK (0xf << 12) 94*4882a593Smuzhiyun #define MXS_DMA_DESC_PIO_WORDS_OFFSET 12 95*4882a593Smuzhiyun #define MXS_DMA_DESC_BYTES_MASK (0xffff << 16) 96*4882a593Smuzhiyun #define MXS_DMA_DESC_BYTES_OFFSET 16 97*4882a593Smuzhiyun 98*4882a593Smuzhiyun struct mxs_dma_cmd { 99*4882a593Smuzhiyun unsigned long next; 100*4882a593Smuzhiyun unsigned long data; 101*4882a593Smuzhiyun union { 102*4882a593Smuzhiyun dma_addr_t address; 103*4882a593Smuzhiyun unsigned long alternate; 104*4882a593Smuzhiyun }; 105*4882a593Smuzhiyun unsigned long pio_words[DMA_PIO_WORDS]; 106*4882a593Smuzhiyun }; 107*4882a593Smuzhiyun 108*4882a593Smuzhiyun /* 109*4882a593Smuzhiyun * MXS DMA command descriptor. 110*4882a593Smuzhiyun * 111*4882a593Smuzhiyun * This structure incorporates an MXS DMA hardware command structure, along 112*4882a593Smuzhiyun * with metadata. 113*4882a593Smuzhiyun */ 114*4882a593Smuzhiyun #define MXS_DMA_DESC_FIRST (1 << 0) 115*4882a593Smuzhiyun #define MXS_DMA_DESC_LAST (1 << 1) 116*4882a593Smuzhiyun #define MXS_DMA_DESC_READY (1 << 31) 117*4882a593Smuzhiyun 118*4882a593Smuzhiyun struct mxs_dma_desc { 119*4882a593Smuzhiyun struct mxs_dma_cmd cmd; 120*4882a593Smuzhiyun unsigned int flags; 121*4882a593Smuzhiyun dma_addr_t address; 122*4882a593Smuzhiyun void *buffer; 123*4882a593Smuzhiyun struct list_head node; 124*4882a593Smuzhiyun } __aligned(MXS_DMA_ALIGNMENT); 125*4882a593Smuzhiyun 126*4882a593Smuzhiyun /** 127*4882a593Smuzhiyun * MXS DMA channel 128*4882a593Smuzhiyun * 129*4882a593Smuzhiyun * This structure represents a single DMA channel. The MXS platform code 130*4882a593Smuzhiyun * maintains an array of these structures to represent every DMA channel in the 131*4882a593Smuzhiyun * system (see mxs_dma_channels). 132*4882a593Smuzhiyun */ 133*4882a593Smuzhiyun #define MXS_DMA_FLAGS_IDLE 0 134*4882a593Smuzhiyun #define MXS_DMA_FLAGS_BUSY (1 << 0) 135*4882a593Smuzhiyun #define MXS_DMA_FLAGS_FREE 0 136*4882a593Smuzhiyun #define MXS_DMA_FLAGS_ALLOCATED (1 << 16) 137*4882a593Smuzhiyun #define MXS_DMA_FLAGS_VALID (1 << 31) 138*4882a593Smuzhiyun 139*4882a593Smuzhiyun struct mxs_dma_chan { 140*4882a593Smuzhiyun const char *name; 141*4882a593Smuzhiyun unsigned long dev; 142*4882a593Smuzhiyun struct mxs_dma_device *dma; 143*4882a593Smuzhiyun unsigned int flags; 144*4882a593Smuzhiyun unsigned int active_num; 145*4882a593Smuzhiyun unsigned int pending_num; 146*4882a593Smuzhiyun struct list_head active; 147*4882a593Smuzhiyun struct list_head done; 148*4882a593Smuzhiyun }; 149*4882a593Smuzhiyun 150*4882a593Smuzhiyun struct mxs_dma_desc *mxs_dma_desc_alloc(void); 151*4882a593Smuzhiyun void mxs_dma_desc_free(struct mxs_dma_desc *); 152*4882a593Smuzhiyun int mxs_dma_desc_append(int channel, struct mxs_dma_desc *pdesc); 153*4882a593Smuzhiyun 154*4882a593Smuzhiyun int mxs_dma_go(int chan); 155*4882a593Smuzhiyun void mxs_dma_init(void); 156*4882a593Smuzhiyun int mxs_dma_init_channel(int chan); 157*4882a593Smuzhiyun int mxs_dma_release(int chan); 158*4882a593Smuzhiyun 159*4882a593Smuzhiyun void mxs_dma_circ_start(int chan, struct mxs_dma_desc *pdesc); 160*4882a593Smuzhiyun 161*4882a593Smuzhiyun #endif /* __DMA_H__ */ 162