Searched refs:MSR_F15H_PERF_CTL (Results 1 – 8 of 8) sorted by relevance
543 #define MSR_F15H_PERF_CTL 0xc0010200 macro544 #define MSR_F15H_PERF_CTL0 MSR_F15H_PERF_CTL545 #define MSR_F15H_PERF_CTL1 (MSR_F15H_PERF_CTL + 2)546 #define MSR_F15H_PERF_CTL2 (MSR_F15H_PERF_CTL + 4)547 #define MSR_F15H_PERF_CTL3 (MSR_F15H_PERF_CTL + 6)548 #define MSR_F15H_PERF_CTL4 (MSR_F15H_PERF_CTL + 8)549 #define MSR_F15H_PERF_CTL5 (MSR_F15H_PERF_CTL + 10)
84 if (msr >= MSR_F15H_PERF_CTL) in nmi_evntsel_msr_to_bit()85 return (msr - MSR_F15H_PERF_CTL) >> 1; in nmi_evntsel_msr_to_bit()
78 amd_ctrls_base = MSR_F15H_PERF_CTL; in xen_pmu_arch_init()124 return MSR_F15H_PERF_CTL + (addr - MSR_K7_EVNTSEL0); in get_fam15h_addr()134 if ((msr >= MSR_F15H_PERF_CTL && in is_amd_pmu_msr()
71 return MSR_F15H_PERF_CTL; in get_msr_base()
281 #define MSR_F15H_PERF_CTL 0xc0010200 macro
316 msrs->controls[i].addr = MSR_F15H_PERF_CTL + (i << 1); in op_amd_fill_in_addresses()
957 x86_pmu.eventsel = MSR_F15H_PERF_CTL; in amd_core_pmu_init()