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Searched refs:KS2_DDR3APLLCTL1 (Results 1 – 3 of 3) sorted by relevance

/OK3568_Linux_fs/u-boot/arch/arm/mach-keystone/
H A Dddr3.c364 tmp = readl(KS2_DDR3APLLCTL1); in ddr3_reset_ddrphy()
366 writel(tmp, KS2_DDR3APLLCTL1); in ddr3_reset_ddrphy()
372 tmp = readl(KS2_DDR3APLLCTL1); in ddr3_reset_ddrphy()
374 __raw_writel(tmp, KS2_DDR3APLLCTL1); in ddr3_reset_ddrphy()
H A Dclock.c32 [DDR3A_PLL] = {KS2_DDR3APLLCTL0, KS2_DDR3APLLCTL1},
/OK3568_Linux_fs/u-boot/arch/arm/mach-keystone/include/mach/
H A Dhardware.h180 #define KS2_DDR3APLLCTL1 (KS2_DEVICE_STATE_CTRL_BASE + 0x364) macro