Searched refs:IPI (Results 1 – 25 of 33) sorted by relevance
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1 Xilinx IPI Mailbox Controller4 The Xilinx IPI(Inter Processor Interrupt) mailbox controller is to manage5 messaging between two Xilinx Zynq UltraScale+ MPSoC IPI agents. Each IPI9 | Xilinx ZynqMP IPI Controller |21 Hardware | | IPI Agent | | IPI Buffers | |26 | Xilinx IPI Agent Block |34 IPI agent node:39 - xlnx,ipi-id: local Xilinx IPI agent ID40 - #address-cells: number of address cells of internal IPI mailbox nodes41 - #size-cells: number of size cells of internal IPI mailbox nodes[all …]
47 order to perform some KVM maintenance. To do so, an IPI is sent, forcing53 1) Send an IPI. This forces a guest mode exit.68 as well as to avoid sending unnecessary IPIs (see "IPI Reduction"), and69 even to ensure IPI acknowledgements are waited upon (see "Waiting for158 then the caller will wait for each VCPU to acknowledge its IPI before160 If, for example, the VCPU is sleeping, so no IPI is necessary, then190 kick will send an IPI to force an exit from guest mode when necessary.195 enter guest mode. This means that an optimized implementation (see "IPI196 Reduction") must be certain when it's safe to not send the IPI. One206 !kvm_request_pending() on its last check and then not receiving an IPI for[all …]
166 :Purpose: Hypercall used to yield if the IPI target vCPU is preempted170 :Usage example: When sending a call-function IPI-many to vCPUs, yield if171 any of the IPI target vCPUs was preempted.
11 # when returning from IPI handler, and when returning to user-space.15 # x86-32 uses IRET as return from interrupt, which takes care of the IPI.19 # x86-64 uses IRET as return from interrupt, which takes care of the IPI.
50 * Pending IPI (inter-processor interrupt) priority, 8 bits51 Zero is the highest priority, 255 means no IPI is pending.54 Zero means no interrupt pending, 2 means an IPI is pending
61 interrupt of the device being passed-through or the initial IPI ESB
71 non-IPI interrupts to a single CPU at a time (EG: Freescale MPIC).127 2 = MPIC inter-processor interrupt (IPI)130 the MPIC IPI number. The type-specific193 * MPIC IPI interrupts. Note the interrupt
221 bool "Xilinx ZynqMP IPI Mailbox"224 Say yes here to add support for Xilinx IPI mailbox driver.226 between processors with Xilinx ZynqMP IPI. It will place the227 message to the IPI buffer and will access the IPI control
27 each of which results in an IPI to the target CPU.48 The dotted arrows denote indirect action, for example, an IPI55 ``smp_call_function_single()`` to send the CPU an IPI, which96 | IPI the CPU to safely interact with the upcoming |105 | IPI the CPU. |128 that the CPU went idle while the IPI was in flight. If the CPU is idle,142 grace periods. In addition, attempting to IPI offline CPUs will result143 in splats, but failing to IPI online CPUs can result in too-short grace231 For RCU-sched, there is an additional check: If the IPI has interrupted235 For RCU-preempt, there is no specific check for idle in the IPI handler[all …]
339 HAC, IPI, SPDIF, HUDI, I2C, enumerator365 INTC_VECT(HAC, 0x580), INTC_VECT(IPI, 0x5c0),425 DMAC, I2C, HUDI, SPDIF, IPI, HAC, TMU, GPIO } },430 { 0xffe00004, 0, 32, 8, /* INT2PRI1 */ { IPI, SPDIF, HUDI, I2C } },
12 a remote vCPU to avoid sending an IPI (and the associated13 cost of handling the IPI) when performing a wakeup.
50 VECTOR handle_interrupt ; (19) Inter core Interrupt (IPI)52 VECTOR handle_interrupt ; (21) Software Triggered Intr (Self IPI)
45 Example with IPI mailbox method:
25 This use IPI and IPC to communicate with remote processors.
82 # Generic IRQ IPI support
96 performs an IPI to inform all processors about the new mapping. This results
57 1 Soft-irq. Uses IPI to complete IOs across CPU nodes. Simulates the overhead
153 /* IPI called on each CPU. */
288 unless absolutely necessary. Please consider using an IPI to wake up
160 global clock event devices. The support of such hardware would involve IPI
161 CPU awakens, the scheduler will send an IPI that can result in
314 This indicates that CPU 7 has failed to respond to a reschedule IPI.
466 achieved by using an IPI to the local processor.
146 packets have been queued to their backlog queue. The IPI wakes backlog
827 to each of the threads, where the IPI handler will also write