xref: /OK3568_Linux_fs/kernel/drivers/mailbox/Kconfig (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun# SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyunmenuconfig MAILBOX
3*4882a593Smuzhiyun	bool "Mailbox Hardware Support"
4*4882a593Smuzhiyun	help
5*4882a593Smuzhiyun	  Mailbox is a framework to control hardware communication between
6*4882a593Smuzhiyun	  on-chip processors through queued messages and interrupt driven
7*4882a593Smuzhiyun	  signals. Say Y if your platform supports hardware mailboxes.
8*4882a593Smuzhiyun
9*4882a593Smuzhiyunif MAILBOX
10*4882a593Smuzhiyun
11*4882a593Smuzhiyunconfig ARM_MHU
12*4882a593Smuzhiyun	tristate "ARM MHU Mailbox"
13*4882a593Smuzhiyun	depends on ARM_AMBA
14*4882a593Smuzhiyun	help
15*4882a593Smuzhiyun	  Say Y here if you want to build the ARM MHU controller driver.
16*4882a593Smuzhiyun	  The controller has 3 mailbox channels, the last of which can be
17*4882a593Smuzhiyun	  used in Secure mode only.
18*4882a593Smuzhiyun
19*4882a593Smuzhiyunconfig IMX_MBOX
20*4882a593Smuzhiyun	tristate "i.MX Mailbox"
21*4882a593Smuzhiyun	depends on ARCH_MXC || COMPILE_TEST
22*4882a593Smuzhiyun	help
23*4882a593Smuzhiyun	  Mailbox implementation for i.MX Messaging Unit (MU).
24*4882a593Smuzhiyun
25*4882a593Smuzhiyunconfig PLATFORM_MHU
26*4882a593Smuzhiyun	tristate "Platform MHU Mailbox"
27*4882a593Smuzhiyun	depends on OF
28*4882a593Smuzhiyun	depends on HAS_IOMEM
29*4882a593Smuzhiyun	help
30*4882a593Smuzhiyun	  Say Y here if you want to build a platform specific variant MHU
31*4882a593Smuzhiyun	  controller driver.
32*4882a593Smuzhiyun	  The controller has a maximum of 3 mailbox channels, the last of
33*4882a593Smuzhiyun	  which can be used in Secure mode only.
34*4882a593Smuzhiyun
35*4882a593Smuzhiyunconfig PL320_MBOX
36*4882a593Smuzhiyun	bool "ARM PL320 Mailbox"
37*4882a593Smuzhiyun	depends on ARM_AMBA
38*4882a593Smuzhiyun	help
39*4882a593Smuzhiyun	  An implementation of the ARM PL320 Interprocessor Communication
40*4882a593Smuzhiyun	  Mailbox (IPCM), tailored for the Calxeda Highbank. It is used to
41*4882a593Smuzhiyun	  send short messages between Highbank's A9 cores and the EnergyCore
42*4882a593Smuzhiyun	  Management Engine, primarily for cpufreq. Say Y here if you want
43*4882a593Smuzhiyun	  to use the PL320 IPCM support.
44*4882a593Smuzhiyun
45*4882a593Smuzhiyunconfig ARMADA_37XX_RWTM_MBOX
46*4882a593Smuzhiyun	tristate "Armada 37xx rWTM BIU Mailbox"
47*4882a593Smuzhiyun	depends on ARCH_MVEBU || COMPILE_TEST
48*4882a593Smuzhiyun	depends on OF
49*4882a593Smuzhiyun	help
50*4882a593Smuzhiyun	  Mailbox implementation for communication with the the firmware
51*4882a593Smuzhiyun	  running on the Cortex-M3 rWTM secure processor of the Armada 37xx
52*4882a593Smuzhiyun	  SOC. Say Y here if you are building for such a device (for example
53*4882a593Smuzhiyun	  the Turris Mox router).
54*4882a593Smuzhiyun
55*4882a593Smuzhiyunconfig OMAP2PLUS_MBOX
56*4882a593Smuzhiyun	tristate "OMAP2+ Mailbox framework support"
57*4882a593Smuzhiyun	depends on ARCH_OMAP2PLUS || ARCH_K3
58*4882a593Smuzhiyun	help
59*4882a593Smuzhiyun	  Mailbox implementation for OMAP family chips with hardware for
60*4882a593Smuzhiyun	  interprocessor communication involving DSP, IVA1.0 and IVA2 in
61*4882a593Smuzhiyun	  OMAP2/3; or IPU, IVA HD and DSP in OMAP4/5. Say Y here if you
62*4882a593Smuzhiyun	  want to use OMAP2+ Mailbox framework support.
63*4882a593Smuzhiyun
64*4882a593Smuzhiyunconfig OMAP_MBOX_KFIFO_SIZE
65*4882a593Smuzhiyun	int "Mailbox kfifo default buffer size (bytes)"
66*4882a593Smuzhiyun	depends on OMAP2PLUS_MBOX
67*4882a593Smuzhiyun	default 256
68*4882a593Smuzhiyun	help
69*4882a593Smuzhiyun	  Specify the default size of mailbox's kfifo buffers (bytes).
70*4882a593Smuzhiyun	  This can also be changed at runtime (via the mbox_kfifo_size
71*4882a593Smuzhiyun	  module parameter).
72*4882a593Smuzhiyun
73*4882a593Smuzhiyunconfig ROCKCHIP_MBOX
74*4882a593Smuzhiyun	tristate "Rockchip Soc Integrated Mailbox Support"
75*4882a593Smuzhiyun	depends on ARCH_ROCKCHIP || COMPILE_TEST
76*4882a593Smuzhiyun	help
77*4882a593Smuzhiyun	  This driver provides support for inter-processor communication
78*4882a593Smuzhiyun	  between CPU cores and MCU processor on Some Rockchip SOCs.
79*4882a593Smuzhiyun	  Please check it that the Soc you use have Mailbox hardware.
80*4882a593Smuzhiyun	  Say Y here if you want to use the Rockchip Mailbox support.
81*4882a593Smuzhiyun
82*4882a593Smuzhiyunconfig PCC
83*4882a593Smuzhiyun	bool "Platform Communication Channel Driver"
84*4882a593Smuzhiyun	depends on ACPI
85*4882a593Smuzhiyun	default n
86*4882a593Smuzhiyun	help
87*4882a593Smuzhiyun	  ACPI 5.0+ spec defines a generic mode of communication
88*4882a593Smuzhiyun	  between the OS and a platform such as the BMC. This medium
89*4882a593Smuzhiyun	  (PCC) is typically used by CPPC (ACPI CPU Performance management),
90*4882a593Smuzhiyun	  RAS (ACPI reliability protocol) and MPST (ACPI Memory power
91*4882a593Smuzhiyun	  states). Select this driver if your platform implements the
92*4882a593Smuzhiyun	  PCC clients mentioned above.
93*4882a593Smuzhiyun
94*4882a593Smuzhiyunconfig ALTERA_MBOX
95*4882a593Smuzhiyun	tristate "Altera Mailbox"
96*4882a593Smuzhiyun	depends on HAS_IOMEM
97*4882a593Smuzhiyun	help
98*4882a593Smuzhiyun	  An implementation of the Altera Mailbox soft core. It is used
99*4882a593Smuzhiyun	  to send message between processors. Say Y here if you want to use the
100*4882a593Smuzhiyun	  Altera mailbox support.
101*4882a593Smuzhiyun
102*4882a593Smuzhiyunconfig BCM2835_MBOX
103*4882a593Smuzhiyun	tristate "BCM2835 Mailbox"
104*4882a593Smuzhiyun	depends on ARCH_BCM2835
105*4882a593Smuzhiyun	help
106*4882a593Smuzhiyun	  An implementation of the BCM2385 Mailbox.  It is used to invoke
107*4882a593Smuzhiyun	  the services of the Videocore. Say Y here if you want to use the
108*4882a593Smuzhiyun	  BCM2835 Mailbox.
109*4882a593Smuzhiyun
110*4882a593Smuzhiyunconfig STI_MBOX
111*4882a593Smuzhiyun	tristate "STI Mailbox framework support"
112*4882a593Smuzhiyun	depends on ARCH_STI && OF
113*4882a593Smuzhiyun	help
114*4882a593Smuzhiyun	  Mailbox implementation for STMicroelectonics family chips with
115*4882a593Smuzhiyun	  hardware for interprocessor communication.
116*4882a593Smuzhiyun
117*4882a593Smuzhiyunconfig TI_MESSAGE_MANAGER
118*4882a593Smuzhiyun	tristate "Texas Instruments Message Manager Driver"
119*4882a593Smuzhiyun	depends on ARCH_KEYSTONE || ARCH_K3
120*4882a593Smuzhiyun	help
121*4882a593Smuzhiyun	  An implementation of Message Manager slave driver for Keystone
122*4882a593Smuzhiyun	  and K3 architecture SoCs from Texas Instruments. Message Manager
123*4882a593Smuzhiyun	  is a communication entity found on few of Texas Instrument's keystone
124*4882a593Smuzhiyun	  and K3 architecture SoCs. These may be used for communication between
125*4882a593Smuzhiyun	  multiple processors within the SoC. Select this driver if your
126*4882a593Smuzhiyun	  platform has support for the hardware block.
127*4882a593Smuzhiyun
128*4882a593Smuzhiyunconfig HI3660_MBOX
129*4882a593Smuzhiyun	tristate "Hi3660 Mailbox" if EXPERT
130*4882a593Smuzhiyun	depends on (ARCH_HISI || COMPILE_TEST)
131*4882a593Smuzhiyun	depends on OF
132*4882a593Smuzhiyun	default ARCH_HISI
133*4882a593Smuzhiyun	help
134*4882a593Smuzhiyun	  An implementation of the hi3660 mailbox. It is used to send message
135*4882a593Smuzhiyun	  between application processors and other processors/MCU/DSP. Select
136*4882a593Smuzhiyun	  Y here if you want to use Hi3660 mailbox controller.
137*4882a593Smuzhiyun
138*4882a593Smuzhiyunconfig HI6220_MBOX
139*4882a593Smuzhiyun	tristate "Hi6220 Mailbox" if EXPERT
140*4882a593Smuzhiyun	depends on (ARCH_HISI || COMPILE_TEST)
141*4882a593Smuzhiyun	depends on OF
142*4882a593Smuzhiyun	default ARCH_HISI
143*4882a593Smuzhiyun	help
144*4882a593Smuzhiyun	  An implementation of the hi6220 mailbox. It is used to send message
145*4882a593Smuzhiyun	  between application processors and MCU. Say Y here if you want to
146*4882a593Smuzhiyun	  build Hi6220 mailbox controller driver.
147*4882a593Smuzhiyun
148*4882a593Smuzhiyunconfig MAILBOX_TEST
149*4882a593Smuzhiyun	tristate "Mailbox Test Client"
150*4882a593Smuzhiyun	depends on OF
151*4882a593Smuzhiyun	depends on HAS_IOMEM
152*4882a593Smuzhiyun	help
153*4882a593Smuzhiyun	  Test client to help with testing new Controller driver
154*4882a593Smuzhiyun	  implementations.
155*4882a593Smuzhiyun
156*4882a593Smuzhiyunconfig QCOM_APCS_IPC
157*4882a593Smuzhiyun	tristate "Qualcomm APCS IPC driver"
158*4882a593Smuzhiyun	depends on ARCH_QCOM || COMPILE_TEST
159*4882a593Smuzhiyun	help
160*4882a593Smuzhiyun	  Say y here to enable support for the APCS IPC mailbox driver,
161*4882a593Smuzhiyun	  providing an interface for invoking the inter-process communication
162*4882a593Smuzhiyun	  signals from the application processor to other masters.
163*4882a593Smuzhiyun
164*4882a593Smuzhiyunconfig TEGRA_HSP_MBOX
165*4882a593Smuzhiyun	bool "Tegra HSP (Hardware Synchronization Primitives) Driver"
166*4882a593Smuzhiyun	depends on ARCH_TEGRA
167*4882a593Smuzhiyun	help
168*4882a593Smuzhiyun	  The Tegra HSP driver is used for the interprocessor communication
169*4882a593Smuzhiyun	  between different remote processors and host processors on Tegra186
170*4882a593Smuzhiyun	  and later SoCs. Say Y here if you want to have this support.
171*4882a593Smuzhiyun	  If unsure say N.
172*4882a593Smuzhiyun
173*4882a593Smuzhiyunconfig XGENE_SLIMPRO_MBOX
174*4882a593Smuzhiyun	tristate "APM SoC X-Gene SLIMpro Mailbox Controller"
175*4882a593Smuzhiyun	depends on ARCH_XGENE
176*4882a593Smuzhiyun	help
177*4882a593Smuzhiyun	  An implementation of the APM X-Gene Interprocessor Communication
178*4882a593Smuzhiyun	  Mailbox (IPCM) between the ARM 64-bit cores and SLIMpro controller.
179*4882a593Smuzhiyun	  It is used to send short messages between ARM64-bit cores and
180*4882a593Smuzhiyun	  the SLIMpro Management Engine, primarily for PM. Say Y here if you
181*4882a593Smuzhiyun	  want to use the APM X-Gene SLIMpro IPCM support.
182*4882a593Smuzhiyun
183*4882a593Smuzhiyunconfig BCM_PDC_MBOX
184*4882a593Smuzhiyun	tristate "Broadcom FlexSparx DMA Mailbox"
185*4882a593Smuzhiyun	depends on ARCH_BCM_IPROC || COMPILE_TEST
186*4882a593Smuzhiyun	help
187*4882a593Smuzhiyun	  Mailbox implementation for the Broadcom FlexSparx DMA ring manager,
188*4882a593Smuzhiyun	  which provides access to various offload engines on Broadcom
189*4882a593Smuzhiyun	  SoCs, including FA2/FA+ on Northstar Plus and PDC on Northstar 2.
190*4882a593Smuzhiyun
191*4882a593Smuzhiyunconfig BCM_FLEXRM_MBOX
192*4882a593Smuzhiyun	tristate "Broadcom FlexRM Mailbox"
193*4882a593Smuzhiyun	depends on ARM64
194*4882a593Smuzhiyun	depends on ARCH_BCM_IPROC || COMPILE_TEST
195*4882a593Smuzhiyun	select GENERIC_MSI_IRQ_DOMAIN
196*4882a593Smuzhiyun	default m if ARCH_BCM_IPROC
197*4882a593Smuzhiyun	help
198*4882a593Smuzhiyun	  Mailbox implementation of the Broadcom FlexRM ring manager,
199*4882a593Smuzhiyun	  which provides access to various offload engines on Broadcom
200*4882a593Smuzhiyun	  SoCs. Say Y here if you want to use the Broadcom FlexRM.
201*4882a593Smuzhiyun
202*4882a593Smuzhiyunconfig STM32_IPCC
203*4882a593Smuzhiyun	tristate "STM32 IPCC Mailbox"
204*4882a593Smuzhiyun	depends on MACH_STM32MP157
205*4882a593Smuzhiyun	help
206*4882a593Smuzhiyun	  Mailbox implementation for STMicroelectonics STM32 family chips
207*4882a593Smuzhiyun	  with hardware for Inter-Processor Communication Controller (IPCC)
208*4882a593Smuzhiyun	  between processors. Say Y here if you want to have this support.
209*4882a593Smuzhiyun
210*4882a593Smuzhiyunconfig MTK_CMDQ_MBOX
211*4882a593Smuzhiyun	tristate "MediaTek CMDQ Mailbox Support"
212*4882a593Smuzhiyun	depends on ARCH_MEDIATEK || COMPILE_TEST
213*4882a593Smuzhiyun	select MTK_INFRACFG
214*4882a593Smuzhiyun	help
215*4882a593Smuzhiyun	  Say yes here to add support for the MediaTek Command Queue (CMDQ)
216*4882a593Smuzhiyun	  mailbox driver. The CMDQ is used to help read/write registers with
217*4882a593Smuzhiyun	  critical time limitation, such as updating display configuration
218*4882a593Smuzhiyun	  during the vblank.
219*4882a593Smuzhiyun
220*4882a593Smuzhiyunconfig ZYNQMP_IPI_MBOX
221*4882a593Smuzhiyun	bool "Xilinx ZynqMP IPI Mailbox"
222*4882a593Smuzhiyun	depends on ARCH_ZYNQMP && OF
223*4882a593Smuzhiyun	help
224*4882a593Smuzhiyun	  Say yes here to add support for Xilinx IPI mailbox driver.
225*4882a593Smuzhiyun	  This mailbox driver is used to send notification or short message
226*4882a593Smuzhiyun	  between processors with Xilinx ZynqMP IPI. It will place the
227*4882a593Smuzhiyun	  message to the IPI buffer and will access the IPI control
228*4882a593Smuzhiyun	  registers to kick the other processor or enquire status.
229*4882a593Smuzhiyun
230*4882a593Smuzhiyunconfig SUN6I_MSGBOX
231*4882a593Smuzhiyun	tristate "Allwinner sun6i/sun8i/sun9i/sun50i Message Box"
232*4882a593Smuzhiyun	depends on ARCH_SUNXI || COMPILE_TEST
233*4882a593Smuzhiyun	default ARCH_SUNXI
234*4882a593Smuzhiyun	help
235*4882a593Smuzhiyun	  Mailbox implementation for the hardware message box present in
236*4882a593Smuzhiyun	  various Allwinner SoCs. This mailbox is used for communication
237*4882a593Smuzhiyun	  between the application CPUs and the power management coprocessor.
238*4882a593Smuzhiyun
239*4882a593Smuzhiyunconfig SPRD_MBOX
240*4882a593Smuzhiyun	tristate "Spreadtrum Mailbox"
241*4882a593Smuzhiyun	depends on ARCH_SPRD || COMPILE_TEST
242*4882a593Smuzhiyun	help
243*4882a593Smuzhiyun	  Mailbox driver implementation for the Spreadtrum platform. It is used
244*4882a593Smuzhiyun	  to send message between application processors and MCU. Say Y here if
245*4882a593Smuzhiyun	  you want to build the Spreatrum mailbox controller driver.
246*4882a593Smuzhiyun
247*4882a593Smuzhiyunconfig QCOM_IPCC
248*4882a593Smuzhiyun	bool "Qualcomm Technologies, Inc. IPCC driver"
249*4882a593Smuzhiyun	depends on ARCH_QCOM || COMPILE_TEST
250*4882a593Smuzhiyun	help
251*4882a593Smuzhiyun	  Qualcomm Technologies, Inc. Inter-Processor Communication Controller
252*4882a593Smuzhiyun	  (IPCC) driver for MSM devices. The driver provides mailbox support for
253*4882a593Smuzhiyun	  sending interrupts to the clients. On the other hand, the driver also
254*4882a593Smuzhiyun	  acts as an interrupt controller for receiving interrupts from clients.
255*4882a593Smuzhiyun	  Say Y here if you want to build this driver.
256*4882a593Smuzhiyun
257*4882a593Smuzhiyunendif
258