1*4882a593Smuzhiyun.. SPDX-License-Identifier: GPL-2.0 2*4882a593Smuzhiyun 3*4882a593Smuzhiyun========================= 4*4882a593SmuzhiyunXICS interrupt controller 5*4882a593Smuzhiyun========================= 6*4882a593Smuzhiyun 7*4882a593SmuzhiyunDevice type supported: KVM_DEV_TYPE_XICS 8*4882a593Smuzhiyun 9*4882a593SmuzhiyunGroups: 10*4882a593Smuzhiyun 1. KVM_DEV_XICS_GRP_SOURCES 11*4882a593Smuzhiyun Attributes: 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun One per interrupt source, indexed by the source number. 14*4882a593Smuzhiyun 2. KVM_DEV_XICS_GRP_CTRL 15*4882a593Smuzhiyun Attributes: 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun 2.1 KVM_DEV_XICS_NR_SERVERS (write only) 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun The kvm_device_attr.addr points to a __u32 value which is the number of 20*4882a593Smuzhiyun interrupt server numbers (ie, highest possible vcpu id plus one). 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun Errors: 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun ======= ========================================== 25*4882a593Smuzhiyun -EINVAL Value greater than KVM_MAX_VCPU_ID. 26*4882a593Smuzhiyun -EFAULT Invalid user pointer for attr->addr. 27*4882a593Smuzhiyun -EBUSY A vcpu is already connected to the device. 28*4882a593Smuzhiyun ======= ========================================== 29*4882a593Smuzhiyun 30*4882a593SmuzhiyunThis device emulates the XICS (eXternal Interrupt Controller 31*4882a593SmuzhiyunSpecification) defined in PAPR. The XICS has a set of interrupt 32*4882a593Smuzhiyunsources, each identified by a 20-bit source number, and a set of 33*4882a593SmuzhiyunInterrupt Control Presentation (ICP) entities, also called "servers", 34*4882a593Smuzhiyuneach associated with a virtual CPU. 35*4882a593Smuzhiyun 36*4882a593SmuzhiyunThe ICP entities are created by enabling the KVM_CAP_IRQ_ARCH 37*4882a593Smuzhiyuncapability for each vcpu, specifying KVM_CAP_IRQ_XICS in args[0] and 38*4882a593Smuzhiyunthe interrupt server number (i.e. the vcpu number from the XICS's 39*4882a593Smuzhiyunpoint of view) in args[1] of the kvm_enable_cap struct. Each ICP has 40*4882a593Smuzhiyun64 bits of state which can be read and written using the 41*4882a593SmuzhiyunKVM_GET_ONE_REG and KVM_SET_ONE_REG ioctls on the vcpu. The 64 bit 42*4882a593Smuzhiyunstate word has the following bitfields, starting at the 43*4882a593Smuzhiyunleast-significant end of the word: 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun* Unused, 16 bits 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun* Pending interrupt priority, 8 bits 48*4882a593Smuzhiyun Zero is the highest priority, 255 means no interrupt is pending. 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun* Pending IPI (inter-processor interrupt) priority, 8 bits 51*4882a593Smuzhiyun Zero is the highest priority, 255 means no IPI is pending. 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun* Pending interrupt source number, 24 bits 54*4882a593Smuzhiyun Zero means no interrupt pending, 2 means an IPI is pending 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun* Current processor priority, 8 bits 57*4882a593Smuzhiyun Zero is the highest priority, meaning no interrupts can be 58*4882a593Smuzhiyun delivered, and 255 is the lowest priority. 59*4882a593Smuzhiyun 60*4882a593SmuzhiyunEach source has 64 bits of state that can be read and written using 61*4882a593Smuzhiyunthe KVM_GET_DEVICE_ATTR and KVM_SET_DEVICE_ATTR ioctls, specifying the 62*4882a593SmuzhiyunKVM_DEV_XICS_GRP_SOURCES attribute group, with the attribute number being 63*4882a593Smuzhiyunthe interrupt source number. The 64 bit state word has the following 64*4882a593Smuzhiyunbitfields, starting from the least-significant end of the word: 65*4882a593Smuzhiyun 66*4882a593Smuzhiyun* Destination (server number), 32 bits 67*4882a593Smuzhiyun 68*4882a593Smuzhiyun This specifies where the interrupt should be sent, and is the 69*4882a593Smuzhiyun interrupt server number specified for the destination vcpu. 70*4882a593Smuzhiyun 71*4882a593Smuzhiyun* Priority, 8 bits 72*4882a593Smuzhiyun 73*4882a593Smuzhiyun This is the priority specified for this interrupt source, where 0 is 74*4882a593Smuzhiyun the highest priority and 255 is the lowest. An interrupt with a 75*4882a593Smuzhiyun priority of 255 will never be delivered. 76*4882a593Smuzhiyun 77*4882a593Smuzhiyun* Level sensitive flag, 1 bit 78*4882a593Smuzhiyun 79*4882a593Smuzhiyun This bit is 1 for a level-sensitive interrupt source, or 0 for 80*4882a593Smuzhiyun edge-sensitive (or MSI). 81*4882a593Smuzhiyun 82*4882a593Smuzhiyun* Masked flag, 1 bit 83*4882a593Smuzhiyun 84*4882a593Smuzhiyun This bit is set to 1 if the interrupt is masked (cannot be delivered 85*4882a593Smuzhiyun regardless of its priority), for example by the ibm,int-off RTAS 86*4882a593Smuzhiyun call, or 0 if it is not masked. 87*4882a593Smuzhiyun 88*4882a593Smuzhiyun* Pending flag, 1 bit 89*4882a593Smuzhiyun 90*4882a593Smuzhiyun This bit is 1 if the source has a pending interrupt, otherwise 0. 91*4882a593Smuzhiyun 92*4882a593SmuzhiyunOnly one XICS instance may be created per VM. 93