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Searched refs:IMX_PLL_BASE (Results 1 – 6 of 6) sorted by relevance

/OK3568_Linux_fs/u-boot/arch/arm/cpu/arm926ejs/mx27/
H A Dgeneric.c47 struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE; in clk_in_26m()
59 struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE; in imx_get_mpllclk()
73 struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE; in imx_get_armclk()
88 struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE; in imx_get_ahbclk()
100 struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE; in imx_get_spllclk()
119 struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE; in imx_get_perclk1()
126 struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE; in imx_get_perclk2()
133 struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE; in imx_get_perclk3()
140 struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE; in imx_get_perclk4()
182 struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE; in cpu_eth_init()
H A Dtimer.c92 struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE; in timer_init()
/OK3568_Linux_fs/u-boot/arch/arm/lib/
H A Dasm-offsets.c81 DEFINE(CSCR, IMX_PLL_BASE + offsetof(struct pll_regs, cscr)); in main()
82 DEFINE(MPCTL0, IMX_PLL_BASE + offsetof(struct pll_regs, mpctl0)); in main()
83 DEFINE(SPCTL0, IMX_PLL_BASE + offsetof(struct pll_regs, spctl0)); in main()
84 DEFINE(PCDR0, IMX_PLL_BASE + offsetof(struct pll_regs, pcdr0)); in main()
85 DEFINE(PCDR1, IMX_PLL_BASE + offsetof(struct pll_regs, pcdr1)); in main()
86 DEFINE(PCCR0, IMX_PLL_BASE + offsetof(struct pll_regs, pccr0)); in main()
87 DEFINE(PCCR1, IMX_PLL_BASE + offsetof(struct pll_regs, pccr1)); in main()
/OK3568_Linux_fs/u-boot/arch/arm/include/asm/arch-imx/
H A Dimx-regs.h49 #define IMX_PLL_BASE (0x1B000 + IMX_IO_BASE) macro
92 #define CSCR __REG(IMX_PLL_BASE) /* Clock Source Control Register */
101 #define MPCTL0 __REG(IMX_PLL_BASE + 0x4) /* MCU PLL Control Register 0 */
102 #define MPCTL1 __REG(IMX_PLL_BASE + 0x8) /* MCU PLL and System Clock Register 1 */
103 #define SPCTL0 __REG(IMX_PLL_BASE + 0xc) /* System PLL Control Register 0 */
104 #define SPCTL1 __REG(IMX_PLL_BASE + 0x10) /* System PLL Control Register 1 */
105 #define PCDR __REG(IMX_PLL_BASE + 0x20) /* Peripheral Clock Divider Register */
/OK3568_Linux_fs/u-boot/board/armadeus/apf27/
H A Dfpga.c194 struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE; in apf27_fpga_setup()
/OK3568_Linux_fs/u-boot/arch/arm/include/asm/arch-mx27/
H A Dimx-regs.h196 #define IMX_PLL_BASE (0x27000 + IMX_IO_BASE) macro