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Searched refs:HHI_HDMI_CLK_CNTL (Results 1 – 8 of 8) sorted by relevance

/OK3568_Linux_fs/kernel/drivers/gpu/drm/meson/
H A Dmeson_vclk.c89 #define HHI_HDMI_CLK_CNTL 0x1cc /* 0x73 offset in data sheet */ macro
817 regmap_update_bits(priv->hhi, HHI_HDMI_CLK_CNTL, in meson_vclk_set()
819 regmap_update_bits(priv->hhi, HHI_HDMI_CLK_CNTL, in meson_vclk_set()
821 regmap_update_bits(priv->hhi, HHI_HDMI_CLK_CNTL, in meson_vclk_set()
898 regmap_update_bits(priv->hhi, HHI_HDMI_CLK_CNTL, in meson_vclk_set()
907 regmap_update_bits(priv->hhi, HHI_HDMI_CLK_CNTL, in meson_vclk_set()
916 regmap_update_bits(priv->hhi, HHI_HDMI_CLK_CNTL, in meson_vclk_set()
925 regmap_update_bits(priv->hhi, HHI_HDMI_CLK_CNTL, in meson_vclk_set()
934 regmap_update_bits(priv->hhi, HHI_HDMI_CLK_CNTL, in meson_vclk_set()
H A Dmeson_dw_hdmi.c108 #define HHI_HDMI_CLK_CNTL 0x1cc /* 0x73 */ macro
440 regmap_update_bits(priv->hhi, HHI_HDMI_CLK_CNTL, 0xffff, 0x100); in dw_hdmi_phy_init()
906 regmap_update_bits(priv->hhi, HHI_HDMI_CLK_CNTL, 0xffff, 0x100); in meson_dw_hdmi_init()
/OK3568_Linux_fs/kernel/drivers/clk/meson/
H A Dmeson8b.h45 #define HHI_HDMI_CLK_CNTL 0x1cc /* 0x73 offset in data sheet */ macro
H A Dgxbb.h57 #define HHI_HDMI_CLK_CNTL 0x1CC /* 0x73 offset in data sheet */ macro
H A Dg12a.h74 #define HHI_HDMI_CLK_CNTL 0x1CC macro
H A Dgxbb.c2317 .offset = HHI_HDMI_CLK_CNTL,
2412 .offset = HHI_HDMI_CLK_CNTL,
2428 .offset = HHI_HDMI_CLK_CNTL,
2443 .offset = HHI_HDMI_CLK_CNTL,
H A Dmeson8b.c1645 .offset = HHI_HDMI_CLK_CNTL,
1746 .offset = HHI_HDMI_CLK_CNTL,
1767 .offset = HHI_HDMI_CLK_CNTL,
1784 .offset = HHI_HDMI_CLK_CNTL,
H A Dg12a.c3583 .offset = HHI_HDMI_CLK_CNTL,
3672 .offset = HHI_HDMI_CLK_CNTL,
3688 .offset = HHI_HDMI_CLK_CNTL,
3703 .offset = HHI_HDMI_CLK_CNTL,