1*4882a593Smuzhiyun /* SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (c) 2016 AmLogic, Inc. 4*4882a593Smuzhiyun * Author: Michael Turquette <mturquette@baylibre.com> 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #ifndef __GXBB_H 8*4882a593Smuzhiyun #define __GXBB_H 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun /* 11*4882a593Smuzhiyun * Clock controller register offsets 12*4882a593Smuzhiyun * 13*4882a593Smuzhiyun * Register offsets from the data sheet are listed in comment blocks below. 14*4882a593Smuzhiyun * Those offsets must be multiplied by 4 before adding them to the base address 15*4882a593Smuzhiyun * to get the right value 16*4882a593Smuzhiyun */ 17*4882a593Smuzhiyun #define SCR 0x2C /* 0x0b offset in data sheet */ 18*4882a593Smuzhiyun #define TIMEOUT_VALUE 0x3c /* 0x0f offset in data sheet */ 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun #define HHI_GP0_PLL_CNTL 0x40 /* 0x10 offset in data sheet */ 21*4882a593Smuzhiyun #define HHI_GP0_PLL_CNTL2 0x44 /* 0x11 offset in data sheet */ 22*4882a593Smuzhiyun #define HHI_GP0_PLL_CNTL3 0x48 /* 0x12 offset in data sheet */ 23*4882a593Smuzhiyun #define HHI_GP0_PLL_CNTL4 0x4c /* 0x13 offset in data sheet */ 24*4882a593Smuzhiyun #define HHI_GP0_PLL_CNTL5 0x50 /* 0x14 offset in data sheet */ 25*4882a593Smuzhiyun #define HHI_GP0_PLL_CNTL1 0x58 /* 0x16 offset in data sheet */ 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun #define HHI_XTAL_DIVN_CNTL 0xbc /* 0x2f offset in data sheet */ 28*4882a593Smuzhiyun #define HHI_TIMER90K 0xec /* 0x3b offset in data sheet */ 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun #define HHI_MEM_PD_REG0 0x100 /* 0x40 offset in data sheet */ 31*4882a593Smuzhiyun #define HHI_MEM_PD_REG1 0x104 /* 0x41 offset in data sheet */ 32*4882a593Smuzhiyun #define HHI_VPU_MEM_PD_REG1 0x108 /* 0x42 offset in data sheet */ 33*4882a593Smuzhiyun #define HHI_VIID_CLK_DIV 0x128 /* 0x4a offset in data sheet */ 34*4882a593Smuzhiyun #define HHI_VIID_CLK_CNTL 0x12c /* 0x4b offset in data sheet */ 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun #define HHI_GCLK_MPEG0 0x140 /* 0x50 offset in data sheet */ 37*4882a593Smuzhiyun #define HHI_GCLK_MPEG1 0x144 /* 0x51 offset in data sheet */ 38*4882a593Smuzhiyun #define HHI_GCLK_MPEG2 0x148 /* 0x52 offset in data sheet */ 39*4882a593Smuzhiyun #define HHI_GCLK_OTHER 0x150 /* 0x54 offset in data sheet */ 40*4882a593Smuzhiyun #define HHI_GCLK_AO 0x154 /* 0x55 offset in data sheet */ 41*4882a593Smuzhiyun #define HHI_SYS_OSCIN_CNTL 0x158 /* 0x56 offset in data sheet */ 42*4882a593Smuzhiyun #define HHI_SYS_CPU_CLK_CNTL1 0x15c /* 0x57 offset in data sheet */ 43*4882a593Smuzhiyun #define HHI_SYS_CPU_RESET_CNTL 0x160 /* 0x58 offset in data sheet */ 44*4882a593Smuzhiyun #define HHI_VID_CLK_DIV 0x164 /* 0x59 offset in data sheet */ 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun #define HHI_MPEG_CLK_CNTL 0x174 /* 0x5d offset in data sheet */ 47*4882a593Smuzhiyun #define HHI_AUD_CLK_CNTL 0x178 /* 0x5e offset in data sheet */ 48*4882a593Smuzhiyun #define HHI_VID_CLK_CNTL 0x17c /* 0x5f offset in data sheet */ 49*4882a593Smuzhiyun #define HHI_AUD_CLK_CNTL2 0x190 /* 0x64 offset in data sheet */ 50*4882a593Smuzhiyun #define HHI_VID_CLK_CNTL2 0x194 /* 0x65 offset in data sheet */ 51*4882a593Smuzhiyun #define HHI_SYS_CPU_CLK_CNTL0 0x19c /* 0x67 offset in data sheet */ 52*4882a593Smuzhiyun #define HHI_VID_PLL_CLK_DIV 0x1a0 /* 0x68 offset in data sheet */ 53*4882a593Smuzhiyun #define HHI_AUD_CLK_CNTL3 0x1a4 /* 0x69 offset in data sheet */ 54*4882a593Smuzhiyun #define HHI_MALI_CLK_CNTL 0x1b0 /* 0x6c offset in data sheet */ 55*4882a593Smuzhiyun #define HHI_VPU_CLK_CNTL 0x1bC /* 0x6f offset in data sheet */ 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun #define HHI_HDMI_CLK_CNTL 0x1CC /* 0x73 offset in data sheet */ 58*4882a593Smuzhiyun #define HHI_VDEC_CLK_CNTL 0x1E0 /* 0x78 offset in data sheet */ 59*4882a593Smuzhiyun #define HHI_VDEC2_CLK_CNTL 0x1E4 /* 0x79 offset in data sheet */ 60*4882a593Smuzhiyun #define HHI_VDEC3_CLK_CNTL 0x1E8 /* 0x7a offset in data sheet */ 61*4882a593Smuzhiyun #define HHI_VDEC4_CLK_CNTL 0x1EC /* 0x7b offset in data sheet */ 62*4882a593Smuzhiyun #define HHI_HDCP22_CLK_CNTL 0x1F0 /* 0x7c offset in data sheet */ 63*4882a593Smuzhiyun #define HHI_VAPBCLK_CNTL 0x1F4 /* 0x7d offset in data sheet */ 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun #define HHI_VPU_CLKB_CNTL 0x20C /* 0x83 offset in data sheet */ 66*4882a593Smuzhiyun #define HHI_USB_CLK_CNTL 0x220 /* 0x88 offset in data sheet */ 67*4882a593Smuzhiyun #define HHI_32K_CLK_CNTL 0x224 /* 0x89 offset in data sheet */ 68*4882a593Smuzhiyun #define HHI_GEN_CLK_CNTL 0x228 /* 0x8a offset in data sheet */ 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun #define HHI_PCM_CLK_CNTL 0x258 /* 0x96 offset in data sheet */ 71*4882a593Smuzhiyun #define HHI_NAND_CLK_CNTL 0x25C /* 0x97 offset in data sheet */ 72*4882a593Smuzhiyun #define HHI_SD_EMMC_CLK_CNTL 0x264 /* 0x99 offset in data sheet */ 73*4882a593Smuzhiyun 74*4882a593Smuzhiyun #define HHI_MPLL_CNTL 0x280 /* 0xa0 offset in data sheet */ 75*4882a593Smuzhiyun #define HHI_MPLL_CNTL2 0x284 /* 0xa1 offset in data sheet */ 76*4882a593Smuzhiyun #define HHI_MPLL_CNTL3 0x288 /* 0xa2 offset in data sheet */ 77*4882a593Smuzhiyun #define HHI_MPLL_CNTL4 0x28C /* 0xa3 offset in data sheet */ 78*4882a593Smuzhiyun #define HHI_MPLL_CNTL5 0x290 /* 0xa4 offset in data sheet */ 79*4882a593Smuzhiyun #define HHI_MPLL_CNTL6 0x294 /* 0xa5 offset in data sheet */ 80*4882a593Smuzhiyun #define HHI_MPLL_CNTL7 0x298 /* MP0, 0xa6 offset in data sheet */ 81*4882a593Smuzhiyun #define HHI_MPLL_CNTL8 0x29C /* MP1, 0xa7 offset in data sheet */ 82*4882a593Smuzhiyun #define HHI_MPLL_CNTL9 0x2A0 /* MP2, 0xa8 offset in data sheet */ 83*4882a593Smuzhiyun #define HHI_MPLL_CNTL10 0x2A4 /* MP2, 0xa9 offset in data sheet */ 84*4882a593Smuzhiyun 85*4882a593Smuzhiyun #define HHI_MPLL3_CNTL0 0x2E0 /* 0xb8 offset in data sheet */ 86*4882a593Smuzhiyun #define HHI_MPLL3_CNTL1 0x2E4 /* 0xb9 offset in data sheet */ 87*4882a593Smuzhiyun #define HHI_VDAC_CNTL0 0x2F4 /* 0xbd offset in data sheet */ 88*4882a593Smuzhiyun #define HHI_VDAC_CNTL1 0x2F8 /* 0xbe offset in data sheet */ 89*4882a593Smuzhiyun 90*4882a593Smuzhiyun #define HHI_SYS_PLL_CNTL 0x300 /* 0xc0 offset in data sheet */ 91*4882a593Smuzhiyun #define HHI_SYS_PLL_CNTL2 0x304 /* 0xc1 offset in data sheet */ 92*4882a593Smuzhiyun #define HHI_SYS_PLL_CNTL3 0x308 /* 0xc2 offset in data sheet */ 93*4882a593Smuzhiyun #define HHI_SYS_PLL_CNTL4 0x30c /* 0xc3 offset in data sheet */ 94*4882a593Smuzhiyun #define HHI_SYS_PLL_CNTL5 0x310 /* 0xc4 offset in data sheet */ 95*4882a593Smuzhiyun #define HHI_DPLL_TOP_I 0x318 /* 0xc6 offset in data sheet */ 96*4882a593Smuzhiyun #define HHI_DPLL_TOP2_I 0x31C /* 0xc7 offset in data sheet */ 97*4882a593Smuzhiyun #define HHI_HDMI_PLL_CNTL 0x320 /* 0xc8 offset in data sheet */ 98*4882a593Smuzhiyun #define HHI_HDMI_PLL_CNTL2 0x324 /* 0xc9 offset in data sheet */ 99*4882a593Smuzhiyun #define HHI_HDMI_PLL_CNTL3 0x328 /* 0xca offset in data sheet */ 100*4882a593Smuzhiyun #define HHI_HDMI_PLL_CNTL4 0x32C /* 0xcb offset in data sheet */ 101*4882a593Smuzhiyun #define HHI_HDMI_PLL_CNTL5 0x330 /* 0xcc offset in data sheet */ 102*4882a593Smuzhiyun #define HHI_HDMI_PLL_CNTL6 0x334 /* 0xcd offset in data sheet */ 103*4882a593Smuzhiyun #define HHI_HDMI_PLL_CNTL_I 0x338 /* 0xce offset in data sheet */ 104*4882a593Smuzhiyun #define HHI_HDMI_PLL_CNTL7 0x33C /* 0xcf offset in data sheet */ 105*4882a593Smuzhiyun 106*4882a593Smuzhiyun #define HHI_HDMI_PHY_CNTL0 0x3A0 /* 0xe8 offset in data sheet */ 107*4882a593Smuzhiyun #define HHI_HDMI_PHY_CNTL1 0x3A4 /* 0xe9 offset in data sheet */ 108*4882a593Smuzhiyun #define HHI_HDMI_PHY_CNTL2 0x3A8 /* 0xea offset in data sheet */ 109*4882a593Smuzhiyun #define HHI_HDMI_PHY_CNTL3 0x3AC /* 0xeb offset in data sheet */ 110*4882a593Smuzhiyun 111*4882a593Smuzhiyun #define HHI_VID_LOCK_CLK_CNTL 0x3C8 /* 0xf2 offset in data sheet */ 112*4882a593Smuzhiyun #define HHI_BT656_CLK_CNTL 0x3D4 /* 0xf5 offset in data sheet */ 113*4882a593Smuzhiyun #define HHI_SAR_CLK_CNTL 0x3D8 /* 0xf6 offset in data sheet */ 114*4882a593Smuzhiyun 115*4882a593Smuzhiyun /* 116*4882a593Smuzhiyun * CLKID index values 117*4882a593Smuzhiyun * 118*4882a593Smuzhiyun * These indices are entirely contrived and do not map onto the hardware. 119*4882a593Smuzhiyun * It has now been decided to expose everything by default in the DT header: 120*4882a593Smuzhiyun * include/dt-bindings/clock/gxbb-clkc.h. Only the clocks ids we don't want 121*4882a593Smuzhiyun * to expose, such as the internal muxes and dividers of composite clocks, 122*4882a593Smuzhiyun * will remain defined here. 123*4882a593Smuzhiyun */ 124*4882a593Smuzhiyun /* ID 1 is unused (it was used by the non-existing CLKID_CPUCLK before) */ 125*4882a593Smuzhiyun #define CLKID_MPEG_SEL 10 126*4882a593Smuzhiyun #define CLKID_MPEG_DIV 11 127*4882a593Smuzhiyun #define CLKID_SAR_ADC_DIV 99 128*4882a593Smuzhiyun #define CLKID_MALI_0_DIV 101 129*4882a593Smuzhiyun #define CLKID_MALI_1_DIV 104 130*4882a593Smuzhiyun #define CLKID_CTS_AMCLK_SEL 108 131*4882a593Smuzhiyun #define CLKID_CTS_AMCLK_DIV 109 132*4882a593Smuzhiyun #define CLKID_CTS_MCLK_I958_SEL 111 133*4882a593Smuzhiyun #define CLKID_CTS_MCLK_I958_DIV 112 134*4882a593Smuzhiyun #define CLKID_32K_CLK_SEL 115 135*4882a593Smuzhiyun #define CLKID_32K_CLK_DIV 116 136*4882a593Smuzhiyun #define CLKID_SD_EMMC_A_CLK0_SEL 117 137*4882a593Smuzhiyun #define CLKID_SD_EMMC_A_CLK0_DIV 118 138*4882a593Smuzhiyun #define CLKID_SD_EMMC_B_CLK0_SEL 120 139*4882a593Smuzhiyun #define CLKID_SD_EMMC_B_CLK0_DIV 121 140*4882a593Smuzhiyun #define CLKID_SD_EMMC_C_CLK0_SEL 123 141*4882a593Smuzhiyun #define CLKID_SD_EMMC_C_CLK0_DIV 124 142*4882a593Smuzhiyun #define CLKID_VPU_0_DIV 127 143*4882a593Smuzhiyun #define CLKID_VPU_1_DIV 130 144*4882a593Smuzhiyun #define CLKID_VAPB_0_DIV 134 145*4882a593Smuzhiyun #define CLKID_VAPB_1_DIV 137 146*4882a593Smuzhiyun #define CLKID_HDMI_PLL_PRE_MULT 141 147*4882a593Smuzhiyun #define CLKID_MPLL0_DIV 142 148*4882a593Smuzhiyun #define CLKID_MPLL1_DIV 143 149*4882a593Smuzhiyun #define CLKID_MPLL2_DIV 144 150*4882a593Smuzhiyun #define CLKID_MPLL_PREDIV 145 151*4882a593Smuzhiyun #define CLKID_FCLK_DIV2_DIV 146 152*4882a593Smuzhiyun #define CLKID_FCLK_DIV3_DIV 147 153*4882a593Smuzhiyun #define CLKID_FCLK_DIV4_DIV 148 154*4882a593Smuzhiyun #define CLKID_FCLK_DIV5_DIV 149 155*4882a593Smuzhiyun #define CLKID_FCLK_DIV7_DIV 150 156*4882a593Smuzhiyun #define CLKID_VDEC_1_SEL 151 157*4882a593Smuzhiyun #define CLKID_VDEC_1_DIV 152 158*4882a593Smuzhiyun #define CLKID_VDEC_HEVC_SEL 154 159*4882a593Smuzhiyun #define CLKID_VDEC_HEVC_DIV 155 160*4882a593Smuzhiyun #define CLKID_GEN_CLK_SEL 157 161*4882a593Smuzhiyun #define CLKID_GEN_CLK_DIV 158 162*4882a593Smuzhiyun #define CLKID_FIXED_PLL_DCO 160 163*4882a593Smuzhiyun #define CLKID_HDMI_PLL_DCO 161 164*4882a593Smuzhiyun #define CLKID_HDMI_PLL_OD 162 165*4882a593Smuzhiyun #define CLKID_HDMI_PLL_OD2 163 166*4882a593Smuzhiyun #define CLKID_SYS_PLL_DCO 164 167*4882a593Smuzhiyun #define CLKID_GP0_PLL_DCO 165 168*4882a593Smuzhiyun #define CLKID_VID_PLL_SEL 167 169*4882a593Smuzhiyun #define CLKID_VID_PLL_DIV 168 170*4882a593Smuzhiyun #define CLKID_VCLK_SEL 169 171*4882a593Smuzhiyun #define CLKID_VCLK2_SEL 170 172*4882a593Smuzhiyun #define CLKID_VCLK_INPUT 171 173*4882a593Smuzhiyun #define CLKID_VCLK2_INPUT 172 174*4882a593Smuzhiyun #define CLKID_VCLK_DIV 173 175*4882a593Smuzhiyun #define CLKID_VCLK2_DIV 174 176*4882a593Smuzhiyun #define CLKID_VCLK_DIV2_EN 177 177*4882a593Smuzhiyun #define CLKID_VCLK_DIV4_EN 178 178*4882a593Smuzhiyun #define CLKID_VCLK_DIV6_EN 179 179*4882a593Smuzhiyun #define CLKID_VCLK_DIV12_EN 180 180*4882a593Smuzhiyun #define CLKID_VCLK2_DIV2_EN 181 181*4882a593Smuzhiyun #define CLKID_VCLK2_DIV4_EN 182 182*4882a593Smuzhiyun #define CLKID_VCLK2_DIV6_EN 183 183*4882a593Smuzhiyun #define CLKID_VCLK2_DIV12_EN 184 184*4882a593Smuzhiyun #define CLKID_CTS_ENCI_SEL 195 185*4882a593Smuzhiyun #define CLKID_CTS_ENCP_SEL 196 186*4882a593Smuzhiyun #define CLKID_CTS_VDAC_SEL 197 187*4882a593Smuzhiyun #define CLKID_HDMI_TX_SEL 198 188*4882a593Smuzhiyun #define CLKID_HDMI_SEL 203 189*4882a593Smuzhiyun #define CLKID_HDMI_DIV 204 190*4882a593Smuzhiyun 191*4882a593Smuzhiyun #define NR_CLKS 207 192*4882a593Smuzhiyun 193*4882a593Smuzhiyun /* include the CLKIDs that have been made part of the DT binding */ 194*4882a593Smuzhiyun #include <dt-bindings/clock/gxbb-clkc.h> 195*4882a593Smuzhiyun 196*4882a593Smuzhiyun #endif /* __GXBB_H */ 197