Searched refs:GET_TOPOLOGY_NUM_OF_BUSES (Results 1 – 6 of 6) sorted by relevance
111 bus_per_interface = GET_TOPOLOGY_NUM_OF_BUSES(); in ddr3_tip_static_round_trip_arr_build()167 bus_per_interface = GET_TOPOLOGY_NUM_OF_BUSES(); in ddr3_tip_write_leveling_static_config()224 u32 bus_per_interface = GET_TOPOLOGY_NUM_OF_BUSES(); in ddr3_tip_read_leveling_static_config()
272 for (bus_cnt = 0; bus_cnt < GET_TOPOLOGY_NUM_OF_BUSES(); bus_cnt++) { in calc_cs_num()335 bus_index < GET_TOPOLOGY_NUM_OF_BUSES(); in hws_ddr3_tip_init_controller()469 bus_cnt < GET_TOPOLOGY_NUM_OF_BUSES(); in hws_ddr3_tip_init_controller()728 for (bus_cnt = 1; bus_cnt < GET_TOPOLOGY_NUM_OF_BUSES(); bus_cnt++) { in ddr3_tip_rank_control()763 for (bus_cnt = 0; bus_cnt < GET_TOPOLOGY_NUM_OF_BUSES(); bus_cnt++) { in ddr3_tip_pad_inv()993 for (bus_index = 0; bus_index < GET_TOPOLOGY_NUM_OF_BUSES(); in ddr3_tip_bus_read()1180 for (bus_cnt = 0; bus_cnt < GET_TOPOLOGY_NUM_OF_BUSES(); bus_cnt++) { in adll_calibration()1302 for (bus_index = 0; bus_index < GET_TOPOLOGY_NUM_OF_BUSES(); in ddr3_tip_freq_set()1431 for (bus_cnt = 0; bus_cnt < GET_TOPOLOGY_NUM_OF_BUSES(); in ddr3_tip_freq_set()2456 for (bus_index = 0; bus_index < GET_TOPOLOGY_NUM_OF_BUSES(); in ddr3_tip_enable_init_sequence()
39 #define GET_TOPOLOGY_NUM_OF_BUSES() \ macro
769 for (bus_cnt = 0; bus_cnt < GET_TOPOLOGY_NUM_OF_BUSES(); in ddr3_tip_print_adll()
1183 for (bus_cnt = 0; bus_cnt < GET_TOPOLOGY_NUM_OF_BUSES(); in ddr3_tip_load_phy_values()
1316 for (bus_id = 0; bus_id < GET_TOPOLOGY_NUM_OF_BUSES(); in ddr3_tip_dynamic_write_leveling_supp()